JPH076033A - Data processor - Google Patents

Abstract

PURPOSE:To eliminate the stop of the execution of a following instruction at the time of a register conflict. CONSTITUTION:When a conflict with a precedent instruction is detected for the 1st time, the memory operated which is used for an arithmetic by the precedent instruction is stored in an associative storage 320 by using the preread address, etc., of the precedent instruction as a key and when a store instruction which updates the memory operand which is used for the arithmetic by the precedent instruction until the precedent instruction is executed next time is executed, the memory operand in the associative storage is replaced with the memory operand generated by the store instruction. When the precedent instruction is preread out of an instruction storage 304 again, the memory operand is read out of the associative storage with the preread address and utilized for the following instruction without waiting for the completion of the arithmetic of the precedent instruction to end. The arithmetic of the read memory operand which is specified with the precedent instruction is performed in the decoding stage of the following instruction by a computing element 360 for conflict elimination and the result is supplied to an address adder and used to calculate the address of the memory operand that the following instruction use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to speeding up an information processing apparatus for pipeline control.

[0002]

2. Description of the Related Art In a pipeline control information processing device,
The entire instruction processing is divided into a plurality of partial processing, and an independent processing device is provided for each partial processing. First, the first instruction is processed by the processing device that performs the first partial processing. When the processing is completed and the processing apparatus for performing the second partial processing is performed, the first
The processing device that performs the partial processing of 2 starts the processing of the second instruction. When the first instruction is transferred to the processing device that performs the third partial processing, the second instruction is processed by the processing device that performs the second partial processing, and the third instruction is processed by the first partial processing device. As described above, since the execution of the subsequent instruction of the first instruction is started before the entire processing of the first instruction is completed, the pipeline control information processing apparatus can realize high instruction processing performance.

As an example of shortening the execution stop due to register conflict, there is JP-A-58-9636.

[0004]

An instruction (hereinafter referred to as a subsequent instruction) before a certain instruction (hereinafter referred to as a subsequent instruction) is an instruction for changing a register, and the subsequent instruction refers to the register. If it is a money instruction (called a register conflict state), the instruction processing does not proceed as described above. That is, until the preceding instruction writes the operation result in the register, or until the preceding instruction generates the operation result, the entire processing of the subsequent instruction, at least the partial processing that refers to the register, must be stopped. In such an information processing device of pipeline control, the suspension of execution of the subsequent instruction in the registration conflict is a major factor for hindering performance improvement.

It is an object of the present invention to provide a pipeline control information processing apparatus which has a high instruction processing performance by eliminating the execution stop of subsequent instructions at the time of register conflict.

[0006]

According to the present invention, when a subsequent instruction is executed by using an operation result written in a register according to the preceding order, the subsequent instruction is processed until the operation result is determined. In the data processing device for stopping the processing using the operation result, the memory operand address of the preceding instruction in association with the associative key associated with the preceding instruction, such as the prefetch address when prefetching the preceding instruction. For storing a memory operand address that matches the store address of the store instruction when the store instruction is executed by the data processing device, and Associative writing means for rewriting the corresponding memory operand with the store data of the store instruction, and the associative key at that time when the preceding instruction is executed Searching said storage means on the basis of, when said associative keys is stored and means for outputting the memory operand corresponding thereto.

[0007]

The above object can be achieved because the processing of the subsequent instruction stopped when the register conflict occurs can be started using the information output from the associative memory.

[0008]

An embodiment of the present invention will be described in detail below with reference to the drawings.

First, the instruction format used in this embodiment will be described with reference to FIG. In this instruction format, each instruction word has a 4-byte length. The first byte represents an opcode (op). The upper 4 bits of the 2nd and 3rd bytes are three register indication fields (R1, X2, B
Represents 3). The lower 4 bits of the 3rd byte and the 4th byte represent the displacement (D2). In this instruction format, each register instruction field has 4 bits, and each has 1 bit.
Point to one of the five registers.

When the instruction is other than the Store instruction, this means that the contents of the general register designated by the X2 field, the contents of the general register designated by the B2 field, and the displacement D.
The sum of 2 is used as an operand address, and the operation code is used for the contents of the location on the main memory pointed to by this address (called the second operand) and the contents of the general-purpose register pointed to by the R1 field (called the first operand). op
Is performed and stored in the general register designated by the R1 field.

When the instruction is a store (Stors) instruction,
Contrary to the above, the contents of the general-purpose register which is the first operand are stored in the location on the main memory which is the second operand.

This instruction format is based on the IBM system (Sy
stem) / 370 instruction format, and more specifically, it is shown in "IBM System / 370 Operations (370 Pronciples of Operation)".

FIG. 1B shows the instructions shown in FIG. 1A in mnemonics.

FIG. 1C is an example of an instruction example causing a register conflict. Pre-order command () is Add
This is an instruction, and means that the contents of register 1, the contents of register 2 and the address obtained by adding displacement 100 are added to the contents of register 5 and stored in register 5. The subsequent instruction () is a subtract instruction, and the contents of register 1 and the contents of register 5 and displacement 1
It means that the content of the address obtained by adding 50 is subtracted from the content of the register 8 and stored in the register 8.

A register conflict occurs because the preceding instruction writes the operation result in the register 5 and the subsequent instruction uses the contents of the register 5.

Next, an outline of the overall configuration of the embodiment will be described with reference to FIGS. When FIG. 2 and FIG. 3 are combined, an overall configuration diagram of the embodiment is obtained. This embodiment uses, as the operation result of the preceding instruction, the operation result of the preceding instruction stored in the associative memory in the previous execution or the result of performing the operation on the second operand of the preceding instruction stored in the associative memory. Is.

First, 304 is an instruction storage device, and 32
6 is an operand storage device. The instruction storage device 304 and the operand storage device are addressed in units of bytes with a 24-bit address.

Reference numeral 100 is a prefetch instruction address register. Instruction prefetching is always performed in units of four instruction words starting from a four instruction word boundary on the instruction storage device. Therefore, the prefetch instruction address register (IFA) 100 stores the upper 20 bits (bit 0-1) of the 24-bit address.
9) is stored.

Reference numeral 102 is a delay register of the prefetch instruction address register.

Reference numerals 104, 106, 108 and 110 denote instruction buffers IB0, IB1, IB2 and IB3, respectively, in which four instruction words prefetched from the instruction storage device 304 are stored in this order.

Reference numeral 112 is an instruction register, and 114 is an instruction counter. One instruction word is always placed in 4 bytes from the instruction word boundary on the instruction storage device. Therefore, the upper 22 bits (bits 0-21) of the 24-bit address are stored in the instruction counter. Instruction counter 1
The value of 14 is the instruction address of the instruction word in the instruction register 112 at that time.

Reference numeral 118 is a register file consisting of 16 registers.

Reference numeral 324 is an address adder, which is the contents of the register designated by the X2 field of the instruction word, that is, X.
The register value indicated by the 2 register value and the B2 field, that is, the B2 register value and the displacement D2 are added. The addition result is stored in the operand address register 120.

Reference numeral 122 is an operand data register, and 330 is an ALU.

124, 130, 132, 134, 136
Are respectively the delay register of the instruction register 122, the delay register of the instruction counter 114, the delay register of the X2 register value, the delay register value of the B2 register value and the delay register of the prefetch instruction address. When the operand address is stored in the operand address register 120, , Instruction register value of the instruction, instruction counter value, X2
The register value, the B2 register value, and the prefetch instruction address when prefetching the instruction are stored.

126, 138, 140, 142, 144
Are registers 124, 130, 132, 134, respectively.
When the operand data register 122 stores operand data, the instruction register value of the instruction, the instruction counter value, the X2 register value, the B2 register value, and the prefetch instruction address at the time of prefetching the instruction, respectively. Stored in.

Reference numeral 320 is an associative storage device, and reference numeral 322 is a register conflict detection device.

Next, the overall operation when there is no register conflict will be described with reference to the overall configuration diagrams of FIGS. 2 and 3 and the timing chart diagram of FIG.

As shown in FIG. 5, it is assumed that the prefetch address register for prefetching the first to fourth instructions is stored in the prefetch address register from time T1. It is also assumed that the instruction register 112 and the instruction counter 114 store the instruction word before the first instruction, that is, the instruction word and instruction address of the 0th instruction before time T2. The address of the prefetch address register 100 is applied to the instruction storage device 304 via the signal line 500, and the four instruction words starting from the address are output to the signal line 506, and the four instructions from the first instruction word to the fourth instruction word. Words are instruction buffers 104, 10 at time T1.
6, 108, and 110.

The address incrementer 302 receives the address of the prefetch address register 100 as an input and outputs the address obtained by incrementing the address by four instruction words from the signal line 502. The signal on the signal line 586, which is the selection signal of the selector 300, is usually the “right selection signal” (when it takes a value other than the “right selection signal”, it is only when explained below). At this time, the signal of the signal line 502 is output to the signal line 506 through the selector 600, and the prefetch address register 100
Stored in. The stored time is time T4, which is four cycles after time T0. Instruction buffers 104, 106, 10
In 8 and 110, these four instruction words are stored until time T5 when the next four instruction words are stored. Prefetch address register 1
Since 00 is usually incremented by 4 instruction words in this way,
In the instruction buffers 104, 106, 108 and 110, the subsequent instructions are prefetched in units of four instructions and stored in sequence.

Before time T2, the instruction counter 1
The instruction address of the 0th instruction was stored in 14. The value of the instruction counter 114 is applied to the address incrementer 310 via the signal line 530, incremented by one instruction word, and becomes the instruction address of the first instruction. Increased value is signal line 5
It is input to the selector 308 via 20. Selector 3
The selection signal 586 of 08 is normally the “right selection signal” as described above, and at this time, the value of the signal line 520 is the selector 20.
It is output to the signal line 518 via the signal line 8. The value of the signal line 518 is stored in the instruction counter 114. Also, the value is applied to the selector 306. The selector 306 looks at the lower 2 bits of the 22-bit address value of the signal line 518, and if it is 0, the data of the signal line 508 is the signal line 5
16 is output, and if it is 1, the data of the signal line 510 is output to the signal line 516. If it is 2, the data on the signal line 512 is output to the signal 516, and if it is 3, the data on the signal line 514 is output to the signal line 516.
As a result, the instruction next to the instruction set at the previous time in the instruction register is selected by the selector 306 and stored in the instruction register 112. At time T2, the first instruction word is stored in the instruction register 112 from the instruction buffer IBO 104, and at the same time, the instruction address of the first instruction is stored in the instruction counter 114.

Further, the value of the prefetch instruction address register is stored in the IFASV register 102 at time T2 which is delayed by two cycles of the prefetch instruction address register IFA100.

A signal line 532 is connected to the selectors 312 and 314.
Register file 1 consisting of 16 registers via
A value of 18 is applied. In the summer, the selector 312 receives the X2 of the first instruction in the instruction register 112 via the signal line 524.
Four bits of field are applied. Thereby, the selector 312 outputs the value of the register designated by the X2 field to the signal line 534. The signal line 52 is connected to the selector 314.
Via 6 the 4 bits of the B2 field of the first instruction in instruction register 112 are applied. Accordingly, the selector 314 outputs the value of the register designated by the B2 field to the signal line 536. Signal lines 592, 590, 593, 5
Normally, "0" is applied to 91 (values other than "0" are applied only in the case described below),
At this time, according to the operation diagram of the selectors 316 and 318 shown in FIG. 10, the value of the signal line 534 is output to the signal line 540 via the selector 316, and the value of the signal line 536 is output to the signal line 542 via the selector 318. Is output.

In this way, the contents of the register designated by the X2 field of the first instruction are input to the address adder via the signal line 540, and the first contents are input via the signal line 542.
The contents of the register designated by the B2 field of the instruction are input. Further, via the signal line 528, the instruction register 11
The displacement D2 of the first command in 2 is input. The address adder adds the above three input values and outputs the operand address of the first instruction, which is the addition result, to the signal line 548, which is stored in the operand address register OA120 at time T3. At the same time, the IR1 register 124 stores the first instruction word via the signal line 522, the IC1 register 130 stores the first instruction address via the signal line 530, and the GRX1 register 132 stores the first instruction word. The X2 register value of the instruction is stored via the signal line 540 and GR
The B2 register value of the first instruction is stored in B1 via the signal line 542, and the prefetch instruction address when the first instruction is prefetched is stored in the IFA1 register 136.

A signal line 55 is provided in the operand storage device 326.
The first in the operand address register 120 through 0
The operand address of the instruction is applied, and the operand data of the first instruction at the location indicated by the address is output to the signal line 552. At time T4,
The operand data of this first instruction is stored in the operand data register 122.

At the same time, the IR2 register 126 stores the first command word from the IR1 register via the signal line 562, and the IC2 register 138 stores the first command word from the IC1 register 130 via the signal line 572. The instruction address is stored, and the signal line 57 is stored in the GRX2 register 140.
0 from the GRX1 register 132 to X2 of the first instruction
The register value is stored, and the GRB2 register 142 stores
First from GRB1 register 134 via signal line 568
The B2 register value of the instruction is stored and IFA2 register 1
44 to the IFA1 register 13 via a signal line 566.
The prefetch instruction address when the first instruction word is prefetched from 6 is stored in the OA2 register 706.
The operand address is stored from the OA register 120 via.

The ALU 330 has three input signal lines. Operand data register 1 from signal line 554
The operand data of the first instruction at 22 is input.
The operation code of the first instruction in the IR2 register 126 is input from the signal line 594. The value of the register file 118 composed of 16 registers is applied to the selector 328 via the signal line 532, and further the R1 field of the first instruction is applied via the signal line 558. As a result, the selector 328 sets the value of the register designated by the R1 field, that is, the R1 register value to the signal line 5.
60, which is input to ALU 330. AL
U uses the input data from the signal line 560 as the first operand data and the input data from the signal line 554 as the second operand data, performs an operation of the operation code indicated by the signal line 594 on both, and outputs the operation result as a signal. Output on line 556.

The register file 118 has a signal line 55.
The operation result of the first instruction is applied via 6 and the signal line 55
R1 of the first instruction in the IR2 register 126 via 8
The field is applied. At time T5, the first
The operation result of the instruction is the register designated by the R1 field,
That is, it is written in the R1 register.

When the instruction is a store instruction, the fact is detected by the write instruction detector 710 and input to the operand storage device 326 via the signal line 712. As a result, when the contents of the R1 register of the store instruction input via the signal line 560 to the operand address of the store instruction input via the signal line 708 in the operand storage device become time T5. Written. At this time, the above-mentioned writing to the R1 register is not performed.

With the above, the processing of the first instruction is completed.

In the processing of the second instruction, first, at time T3, the second instruction word is stored in the instruction register 112, and the instruction address of the second instruction is stored in the instruction counter IC. After that, the first
The process proceeds in the same manner as the instruction.

The processing of the third and subsequent instructions proceeds like the first and second instructions at a time one cycle behind the previous instruction processing.
However, since the prefetch of the instruction is in units of four instruction words, the prefetch instruction address register 100, the instruction buffer 104,
The storage in 106, 108, 110 and the IFASV register 102 is performed once every four cycles.

As described above, when there is no register conflict, instruction processing progresses every cycle.

Next, the overall operation in the case of register conflict will be described. Before that, the associative storage device 320 will be described with reference to FIG.

The storage capacity of the associative memory device in the embodiment is 10 words.

Each word corresponds to the IC storage unit ICP346 and I
R storage unit IRP348 and X2 register value storage unit GRXP35
0 and B2 register value storage unit GRBP352, prefetch instruction address storage unit IFAP354, data storage unit DATAP356, address storage unit ADDRP345, and flag storage unit FLGP347.

Signal lines 530, 522, 540, 542
When data is applied to 500, the associative memory device searches. Data on signal lines 530, 522, 540, 542, 500 and IC storage unit ICP346, IR storage unit IRP
348, X2 register value storage unit GRXP350, B2 register value storage unit GRBP352, prefetch instruction address storage unit IFAP
When there is a word in which the data of 354 all match, the match detector 344 outputs "1" to set the HITL register 156 to "1", and the data storage unit of that word
The data of DATAP 356 is stored in the DATAL register 158, and the data of the flag storage unit FLGP347 is stored in the FLGL register 1
It stores in 57. When there is no matching word, the match detector 344 outputs "0" and sets the HITL register 156 to "0".

On the other hand, the signal line 584 is "1" or the signal line 5
When “0” is applied to 86, the associative memory device outputs the signal lines 580, 564, 578, 576, 574, 55.
The data in the IC storage unit ICP34
6, IR storage unit IRP348, X2 register value storage unit GR
XP350, B2 register value storage unit GRBP352, prefetch instruction address storage IFAP354, data storage unit DATAP 356
A word having "1" in the flag storage unit FLGP347 is registered as the data of the address storage unit ADDRP 345. At that time, the IC storage unit ICP346, the IR storage unit IRP34
8, X2 register value storage unit GRXP350, B2 register value storage unit GRBP352, prefetch instruction address storage unit IFAP35
When a word in which the data of 4 are all the same is already stored, it is overwritten on the word. When the matching word is not yet stored, a new word is assigned and registered.

When "1" is applied to the signal line 712, that is, when the store instruction is executed, the associative memory device sends the operand of the store instruction sent via the signal line 708. Detects whether there is a word whose address and address storage unit ADDRP match, and if so, data storage unit DA for all such words
Store where TAP is transferred via signal line 560
The instruction is rewritten with the contents of the R1 register, and "0" is stored in the flag storage unit FLGP of the word.

Incidentally, "1" in the flag storage unit FLGP means that the operation result when the instruction is previously executed is stored in the corresponding data storage unit DATAP.
"0" of FLGP means that the second operand data is stored in the corresponding data storage unit DATAP.

This is the end of the description of the associative memory device.

Next, the operation when there is a register conflict will be described. 2 are considered as the instruction having the register conflict, the Add instruction is the first instruction, and the Subtract instruction is the second instruction.
The third and subsequent instructions are arbitrary instructions that do not cause register conflict with these instructions.

In the present invention, the operation result of the preceding instruction causing the register conflict (the first instruction in the example considered below) is obtained by using the information stored in the associative memory. Therefore, when executing the preceding instruction, whether or not the prediction can be made depends on whether or not there is information in the associative memory.

First, the case where the associative storage device does not have the information of the previous execution will be described. FIG. 6 is used as a timing chart.

Instruction prefetch from the first instruction to the fourth instruction,
And most of the processing of the first instruction is the same as the operation when there is no register conflict as described above. That is, in the timing chart of FIG. 6, IFA, IBO to 3, IFASV for the first to fourth instructions, IR / IC, OA / IR1 / IC1 / GRX1 / G for the first instruction.
RB1 / IFA1, OD / IR2 / IC2 / GRX2 /
The timing of GRB2 / IFA2, GR is the same as that of FIG. The other parts will be described below.

First, from time TO, the prefetch instruction address stored in the prefetch instruction address register 100 is applied to the prefetch instruction address storage unit IFAP 354 of the associative storage device through the signal line 500. At time T2, the instruction word of the first instruction, the instruction address, the X2 register value, and the B2 register value are transferred to the signal lines 522, 530, respectively.
It is applied to the IR storage unit 348, the IC storage unit 346, the X2 register value storage unit 350, and the B2 register value storage unit 352 of the associative storage device via 540 and 542, respectively.

The associative memory device includes the signal lines 530 and 52.
Search with 2,540,542,500 data. Since it is now considered that the associative storage device does not have information on the previous execution, "0" is stored in the HITL register 156 at time T3. Further, this “0” is the signal line 54
6 is applied.

At time T3, the IR1 register 124 stores the instruction word of the Add instruction which is the first instruction, and the instruction register 112 stores the instruction word of the Subtract instruction which is the second instruction. Therefore, the signal line 58
2 is applied with “5” in the R1 field of the first instruction, and the X2 field “5” of the second instruction is applied to the signal line 524.
Is applied. Since it is assumed that there is no register conflict other than the first instruction and the second instruction, the signal line 558,
A value different from “5” is applied to 526. Therefore, the output of the coincidence comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, 166 are "0".
Becomes Therefore, the output signal line 593 of the OR circuit 168 becomes "1". Further, the output signal line 59 of the OR circuit 170
1, the output signal line 592 of the AND circuit 172, the output signal line 590 of the AND circuit 174, and the output signal line 584 of the AND circuit 180 become “0”.

The signal line 592 is "0", and the signal line 59 is
Since 3 is "1", as shown in FIG. 10, significant data is not output on the signal line 540. On the other hand, the selector 318 applies the B2 register value of the second instruction on the signal line 536 to the address adder 324 via the signal line 542. The displacement of the second command is applied to the address adder from the signal line 528. As a result, at time T4, significant data is not stored in the operand address register 120.

No significant data is stored in the IR1 register 124, the IC1 register 130, the GRX1 register 132, the GRB1 register 134, or the IFA1 register 136.

In the subsequent operation of the second instruction, the signal line 540
The address adder 548 does not output any significant data because no significant data is output above. Therefore, no significant data is stored in the operand address register 120 even at time T4. Also, IR1 register 1
24, IC1 register 130, GRX1 register 13
2, GRB1 register 134, IFA1 register 136
No significant data is stored.

On the other hand, at time T4, the IR2 register 1
26 stores the instruction word of the Add instruction which is the first instruction. At this time, the output of the coincidence comparison circuit 164 becomes "1", and the other coincidence comparison circuits 160, 162, 16
The output of 6 becomes "0". Therefore, the output signal line 593 of the OR circuit 168 and the output signal line 584 of the AND circuit 180 become "1". Further, the output signal lines 591 and 596 of the OR circuits 170 and 182 and the output signal lines 592 and 590 of the AND circuits 172 and 174 become “0”. At this time as well, the signal line 592 is "0" and the signal line 593 is "1", so that no data is output onto the signal line 540. Signal line 5
The address adder 548 does not output significant data because no significant data is output on 40. Therefore, no significant data is stored in the operand address register 120 even at time T5. Further, the IR1 register 124, the IC1 register 130, the GRX1 register 13
2, no significant data is stored in the GRB1 register 134 and the IFA register 136.

On the other hand, at time T5, no significant data is stored in the IR2 register 138. At this time, the outputs of the coincidence comparison circuits 160, 162, 164, 166 are "0". Therefore, the signal lines 590, 591, 592
All of 593, 584 and 596 are “0”.

As a result, the selector 316 causes the signal line 53
The X2 register value of the second address on No. 4 is applied to the address adder 324 via the signal line 540, and the selector 318
Applies the B2 register value of the second address on the signal line 536 from the signal to the address adder 324 via 542. The displacement of the second address is applied to the address adder from the signal line 528. As a result, at time T6,
The operand address of the second address is stored in the operand address register 120.

The IR1 register 124, the IC1 register 130, the GRX1 register 132, the GRB1 register 134, and the IFA register 136 store the same data as that at the time of no register conflict at time T6.

The subsequent operation of the second address proceeds in the same manner as when there is no register conflict.

From time T4, the operation of the first instruction is ALU33.
The calculation result is applied to the associative memory device via the signal line 556 in the middle of time T4 and T5.

Furthermore, "1" on the signal line 584 is applied to the associative memory. As a result, the IC storage unit 346, the IR storage unit 348, the X2 register value storage unit 350, the B2 register value storage unit 352, the prefetch instruction address storage unit 354, the data storage unit 356, and the address storage unit 347 of the associative storage device receive signals. Instruction address of first instruction on line 580, first instruction word on signal line 564, X2 register value of first instruction on signal line 578, B2 register value of first instruction on signal line 576, signal line 574 A word in which the prefetch instruction address at the time of prefetching the above first instruction, the operation result of the first instruction on the signal line 556, the operand address of the first instruction on the signal line 708, and the flag storage unit 347 being "1" Is registered at time T5.

This completes the description of the case where there is no information in the associative memory.

Next, the case where there is information in the associative memory will be described. The associative memory may store the operation result of the preceding instruction at the previous execution time or may store the memory operand of the preceding instruction.

First, the case where the associative memory device has the information result of the previous execution will be described. FIG. 7 is used as a timing chart.

The operation result is obtained by performing an operation on the first operand and the second operand (memory operand) in an operation instruction other than the load instruction. Since the first operand at the previous execution may not match the first operand at the next execution, the operation result in the associative memory cannot be said to be correct. Therefore, in the following cases, the processing of the second instruction is started with the operation result of the associative memory, and when the operation result of the first instruction is obtained later, it is compared with the operation result of the associative memory. The method is to redo the process.

Instruction prefetch from the first instruction to the fourth instruction,
And most of the processing of the first instruction is the same as the operation when there is no register conflict as described above. That is, in the timing chart of FIG. 7, IFA, IBO to 3IFASY for the first to fourth instructions, IR / IC, OA / IR1 / IC1 / GRX1 / GR for the first instruction.
B1 / IFA1, OD / IR2 / IC2 / GRX2 / G
The timing of RB2 / IFA2 and GR is the same as that of FIG. The other parts will be described below.

First, from time TO, the prefetch instruction address stored in the prefetch instruction address register 100 is stored in the prefetch instruction address register 100 to the prefetch instruction address storage unit IFAP 354 of the associative storage device via the signal line 500. Is being applied. Also, at time T2, the instruction word of the first instruction, the instruction address X2 register value, and the B2 register value are changed to signal lines 522, 530, respectively.
It is applied to the IR storage unit 348, the IC storage unit 346, the X2 register value storage unit 350, and the B2 register value storage unit 352 of the associative storage device via 540 and 542, respectively.

The associative memory device includes the signal lines 530 and 52.
Search with 2,540,542,500 data. Since it is now considered that the associative storage device has the information on the previous execution, the DATAL register 158 at time T3.
Stores the previous operation result of the first instruction, FLGL register 157 stores "1", and HITL register 156 stores "1". Furthermore, this "1" is the signal line 54
6 is applied.

At time T3, the IR1 register 124 stores the instruction word of the Add instruction which is the first instruction, and the instruction register 112 stores the instruction word of the Subtract instruction which is the second instruction. Therefore, the signal line 58
2 is applied with “5” in the R1 field of the first instruction, and the X2 field “5” of the second instruction is applied to the signal line 524.
Is applied. Since it is assumed that there is no register conflict other than the first instruction and the second instruction, the signal line 558,
A value different from “5” is applied to 526. Therefore, the output of the coincidence comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, 166 are "0".
Becomes Therefore, it is ORed with the output signal line 593 of the OR circuit 168.
The output signal line 596 of the circuit 182 and the output signal line 172 of the AND circuit 172 become “1”. Also, the output signal line 591 of the OR circuit and the output signal line 59 of the AND circuit 174
0, the output signal line of the AND circuit 180 becomes "0".

The signal line 596 serves as a set signal for the ICSV register 158. Since this signal line is "1", the instruction address of the second instruction is stored in the ICSV register 116 at time T4 and the first signal is stored in the DATASV register 154. The previous operation result of the instruction is stored.

The signal line 592 is "1" and the signal line 71
Since 4 is "1", as shown in FIG.
6 applies the previous operation result of the first instruction on the signal line 538 to the address adder 324 via the signal line 540, and the selector 318 sets the B2 register value of the second instruction on the signal line 536 to the signal line 542. It is applied to the address adder 324 via the address adder 324. The displacement of the second command is applied to the address adder from the signal line 528. As a result, at time T4, the operand address of the second instruction is stored in the operand address register 120.

Further, at the time T4, the same data as the operation when there is no register conflict is stored in the IR1 register 124, the IC1 register 130, the GRX1 register 132, the GRB1 register 134, and the IFA register 136.

The subsequent operation of the second instruction proceeds in the same manner as when there is no register conflict.

From time T4, the operation of the first instruction is ALU33.
The operation result is applied to the comparator 332 via the signal line 556 in the middle of time T4 and T5. The previous operation result of the first instruction stored in the DATASV register 154 is applied to the other input of the comparator 332.

The following operation is divided into two types depending on whether or not the calculation result of the ALU 330 matches the previous calculation result.
First, the case where they match will be described. In this case, the signal line 58
A “1” is applied on 6. This "1" is sector 3
00 and 308. At this time, the selector 300 outputs the data of the signal line 502 to the signal line 506, and the selector 308 outputs the data of the signal line 520 to the signal line 518. This is the same operation as when there is no register conflict, and the subsequent operation proceeds in the same manner as in that case.

A case where the calculation result in the ALU 330 does not match the previous calculation result will be described below. Although FIG. 7 has been used as the timing chart in the above description, FIG. 8 is used in the following description. In this case, the signal line 586
Is applied with "0". This “0” is the selector 300
And 308 are input. At this time, the selector 300 outputs the data of the signal line 504 to the signal line 506, and the selector 3
08 outputs the data of the signal line 504 to the signal line 518. As a result, at time T5, the pre-read instruction address register 100 stores the upper 20 bits of the instruction address of the second instruction stored in the ICSV register 116. This value is the same as the prefetch address from the first instruction to the fourth instruction. As a result, the prefetch is executed, and at time T6, the first to fourth instructions are transferred to the instruction buffer 104,
106, 108, 110. Since the instruction address of the second instruction is applied to the signal line 518, the instruction buffer (T
The second instruction on LB1) 106 is stored. The first instruction that caused a register conflict with the second instruction is time 5
In, the calculation result has already been written in the register designated by the R1 field. Therefore, at the time T7, the procedure is the same as that in the case where there is no register conflict between the first instruction and the second instruction.

Furthermore, "0" on the signal line 586 is applied to the associative memory. As a result, the IC storage unit 346, the IR storage unit 348, the X2 register value storage unit 350, the B2 register value storage unit 352, the prefetch instruction address storage unit 354, the data storage unit 356, and the address storage unit 345 of the associative storage device receive signals. Instruction address of first instruction on line 580, first instruction word on signal line 564, X2 register value of first instruction on signal line 578, B2 register value of first instruction on signal line 576, signal line 574 The word that is the prefetch instruction address at the time of prefetching the first instruction above, the operation result of the first instruction on the signal line 556, the operand address of the first instruction on the signal line 708, and whose flag storage unit is “1” is It is registered at time T5.

This is the end of the explanation in the case where the calculation result in the ALU 330 does not match the previous calculation result.

Furthermore, this concludes the description in the case where the associative memory device has the previous execution operation result.

Consider the following situation. First, the add (Add) instruction and the subtract (Subtract) instruction in FIG. 2 are executed. The above-mentioned register conflict exists between them. The operation result of the add (Add) instruction is stored in the associative memory 320 as described above. Next store (St
ore) instruction is executed. The store address of this instruction is assumed to be the same as the operand address of the add instruction described above. If the contents of the associative memory 320 (that is, the operation result) is not changed at the time of executing this store instruction, the addition (Ad
When the d) instruction and the subtract instruction are executed, the associative memory 320 outputs the operation result of the previous execution of the addition (Add) instruction, which is used in the subtract instruction. Since the operand data used in the second addition (Add) instruction has been changed by the above-mentioned Store instruction, the operation result of the previous execution of the addition (Add) instruction output from the associative memory 320 Does not correctly predict the operation result of the second execution of the add instruction.
Thus, when a Store instruction is executed and its store address is equal to the operand address of the instruction stored in associative memory, the operation result of this instruction stored in associative memory is The result will be different when the instruction is executed after that. Store (Stor
e) When the instruction is executed, the operation result in the associative memory may be rewritten with the store data.

At this time, the content of the associative memory 320 is incorrect when the second Add instruction is executed, as described above, because the second Add instruction is executed after the first Add and Subtract instructions are executed. By the time the instruction is executed,
Since it is only when the operand data of the Add instruction is rewritten by the store instruction, if the operation result of the associative memory 320 is rewritten with the store data, the rewritten data of the associative memory 320 is always correct. The processing will be described below.

As already described in the description of the associative memory device 320, the signal line 71 is generated when the store instruction is executed.
“1” is transferred to the associative memory via 2. At the same time, the operand address (that is, the store address) of the Store instruction is transferred via the signal line 708, and the R1 of the Store instruction is transferred via the signal line 560.
The contents of the register (ie store data) is transferred.

At this time, the associative storage device is the address storage unit AD.
The DR finds all the words having the same store address, rewrites the data of the same word in the storage unit DATAP with the store data, and rewrites the flag storage unit of the word to "0".

This is the end of the description of the processing when the store instruction is executed.

Next, the case where the associative memory device has the second operand (memory operand) of the preceding instruction will be described.
FIG. 7 is used as a timing chart.

In this case, when the store instruction is executed as described above, the data in the associative memory (the operation result before the first instruction or the memory data (the second operand) of the first instruction) is stored as the store data. Since it is being rewritten, the second operand in the associative memory is always correct. Also, in this case, as shown below, for the second operand,
When the instruction is executed, since the operation is performed using the first operand at the time of execution, the operation result is correct, unlike the previous operation result stored in the associative memory. Therefore, in this case, it is not necessary to perform the coincidence comparison between the previous operation result and the operation result in the ALU and the redo process of the second instruction as described above.

Data rewriting in the associative memory 320 by the store data by such a store instruction has not occurred, and the operation result (the operation result of the first Add instruction in the associative memory 320 has not been generated as described above. ), Then 2
R, which is the first operand when the Add instruction is executed for the second time
Since the value of one register may be different from that at the time of the first Add instruction, it is indispensable to compare and compare the previous operation result and the operation result in the ALU 330 and to redo the second instruction (Subtract instruction).

Instruction prefetch from the first instruction to the fourth instruction,
And most of the processing of the first instruction is the same as the operation when there is no register conflict as described above. That is, in the timing chart of FIG.
IFA for instructions, IB0 to 3IFASV, IR / IC for first instruction, OA / IR1 / IC1 / GRX1 / G
RB1 / IFA1, OD / IR2 / IC2 / GRX2 /
The timing of GRB2 / IFA2, GR is the same as that of FIG. The other parts will be described below.

First, from the time TO, the prefetch instruction address stored in the prefetch instruction address register 100 is
It is applied to the prefetch instruction address storage unit IFAP 354 of the associative storage device via the signal line 500. Also, at time T2
Becomes, the instruction word of the first instruction, the instruction address X2 register value, and the B2 register value are signal lines 522, 530, respectively.
It is applied to the IR storage unit 348, the IC storage unit 346, the X2 register value storage unit 350, and the B2 register value storage unit 352 of the associative storage device via 540 and 542, respectively.

The associative memory device includes the signal lines 530 and 52.
Search with 2,540,542,500 data. Since it is now considered that the associative memory device has the second operand (memory operand) of the preceding instruction, the time T3
, The DATAL register 158 stores the first instruction, that is, the second operand of the preceding instruction, and the FLGL register 1
“0” is stored in 57 and “1” is stored in the HITL register 156. Furthermore, this "1" is the signal line 54
6 is applied.

At time T3, the IR1 register 124 stores the instruction word of the Add instruction which is the first instruction, and the instruction register 112 stores the instruction word of the Subtract instruction which is the second instruction. Therefore, the signal line 58
2 is applied with “5” in the R1 field of the first instruction, and the signal line 542 is supplied with “5” in the X2 field of the second instruction.
Is applied. Since it is assumed that there is no register conflict other than the first instruction and the second instruction, the signal line 558,
A value different from “5” is applied to 526. Therefore, the output of the coincidence comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, 166 are "0".
Becomes Therefore, it is ORed with the output signal line 593 of the OR circuit 168.
The output signal line of the circuit 182 and the output signal line 172 of the AND circuit 172 become “1”. The output signal line 591 of the OR circuit and the output signal lines 590, AN of the AND circuit 174 are also provided.
The output signal line of the D circuit 180 becomes "0".

To the ALU 360, the second operand of the first instruction is input via the signal line 538, the contents of the R1 register of the first instruction, that is, the first operand is input via the signal line 606, and the signal line 604 is input. The operation code of the first instruction is input via the. The ALU 360 is now the first
The instruction is calculated and the calculation result is output to the signal line 600.

The signal line 592 is "1" and the signal line 71
Since 4 is "0", the selector 31 as shown in FIG.
6 is a calculation result of the first command on the signals 600
It is applied to the address adder 324 via 0, and the selector 3
18 applies the B2 register value of the second instruction on the signal line 536 to the address adder 324 via the signal line 542.
The displacement of the second command is applied to the address adder from the signal line 528. As a result, at time T4, the second instruction operand address becomes the operand address register 12
Stored in 0.

The IR1 register 124, the IC1 register 130, the GRX register 132, the GRB1 register 134, and the IFA1 register 136 store the same data as the operation when there is no register conflict at time T4.

The subsequent operation of the second instruction proceeds in the same manner as when there is no register conflict.

This completes the description of the case where the associative memory device has the second operand of the preceding instruction.

Next, the effects peculiar to this embodiment will be described.

In the case where the present invention is not used, when the preceding instruction and the subsequent instruction having a register conflict are executed, the same operation as the case where the associative memory device of the above-mentioned operation explanation does not have the information of the previous execution is performed, and the empty time of two cycles is obtained. Cause

The use of the present invention eliminates any vacant time, which improves the instruction processing performance when a register conflict occurs.

In the above-described embodiment, as the operation result of the preceding instruction, the previous operation result of the preceding instruction stored in the associative memory or the second operation of the preceding instruction stored in the associative memory is used.
The result obtained by performing the operation on the operand (memory operand) using the first operand of the preceding instruction is used. However, in the present invention, the previous operation result of the preceding instruction is not stored in the associative memory, but the second operand of the preceding instruction is always stored, and the operation result of the preceding instruction always precedes the second operand. It can also be applied to the case where the result obtained by performing the operation using the first operand of the instruction is used.

An embodiment in this case is shown in FIGS.

In the associative memory of this figure, when there is no information in the associative memory, the second operand of the preceding instruction is stored via the signal line 554 instead of the signal line 556 of FIG. ". By doing so, the second operand of the preceding instruction is always stored in the associative memory. Therefore,
When the second operand is stored in the associative memory, the subsequent instruction can be executed without any free time as in the above-mentioned embodiment.

Further, in the two embodiments shown in FIGS. 2, 3 and 11 and 12, when the store instruction is executed, the store
The information in the associative memory is rewritten using the data. However, when the store instruction is executed, the present invention
It can also be applied to invalidate a word whose address and operand address match.

In this case, the associative memory 320 shown in FIG.
When “1” is applied to the signal line 712,
A word having the same address as the store address on 08 may be deleted from the associative memory. Also in this case, when the information is stored in the associative memory,
Subsequent instructions can be executed without any free time as in the above embodiment.

Further, as the associative key, all of the above-mentioned can be used, or an arbitrary combination can be used. It is also possible to use some bit positions of the key component.

[0113]

If the present invention is not used, the address calculation time of the preceding instruction, the operand read time, and the operation time are required from the start of the preceding instruction causing the register conflict to the start of the succeeding instruction.

However, by using the present invention, it takes only the time from the input of the associative key to the prediction device to the output of the prediction value. The latter time depends on what is used for the associative key, but in the worst case where the instruction address of the preceding instruction is used for the associative key, the time is sufficiently shorter than that without the present invention.

[Brief description of drawings]

1A is an instruction format diagram, FIG. 1B is an example of a load instruction, and FIG. 1C is an example of two instructions that cause a register conflict.

FIG. 2 is a diagram showing a part of the overall configuration of the first embodiment.

FIG. 3 is a diagram showing the remaining portion of the first embodiment.

FIG. 4 is a configuration diagram of an associative storage device used in the first embodiment.

FIG. 5 is a timing chart of the operation of the first embodiment.

FIG. 6 is another timing chart of the first embodiment.

FIG. 7 is another timing chart of the first embodiment.

FIG. 8 is still another timing chart of the first embodiment.

FIG. 9 is a configuration diagram of a register conflict detection device according to the first embodiment.

FIG. 10 is an operation diagram of the selector according to the first embodiment.

FIG. 11 is a diagram showing a part of the overall configuration of the second embodiment.

FIG. 12 is a diagram showing the remaining portion of the second embodiment.

[Explanation of symbols]

100 ... Prefetch instruction address register, 304 ... Instruction storage device, 104, 106, 108, 110 ... Instruction buffer, 112 ... Instruction register, 114 ... Instruction counter, 3
24 ... Address adder, 120 ... Operand address register, 326 ... Operand storage device, 126 ... Operand data register, 330 ... ALU, 118 ... Register file, 320 ... Associative storage, 322 ... Register conflict detection device.

Front page continuation (72) Inventor Eiki Kamata 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shigeo Takeuchi 1479, Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra Els In-house Engineering Co., Ltd.

Claims (1)

[Claims] 1. When a subsequent instruction is executed by using the operation result written in a register according to the preceding order, the subsequent instruction is processed until the operation result is determined, and the operation result is used. In the data processing device for stopping the preceding instruction, means for storing the memory operand address of the preceding instruction in association with the associative key associated with the preceding instruction, such as the prefetch address when prefetching the preceding instruction, When a store instruction is executed by the data processing device, it is searched whether the memory operand address matching the store address of the store instruction is present in the storage means, and at some time, the corresponding memory operand address is searched. Associative writing means for rewriting with store data of the store instruction, and searching the storage means based on the associative key at the time when the preceding instruction is executed. And, a data processing device and means for outputting the memory operand corresponding thereto when said associative keys is stored.