JPH04245333A - Information processor - Google Patents

Abstract

PURPOSE:To execute an instruction right after an instruction, which switches register windows, in parallel by an information processor which has plural window registers. CONSTITUTION:For example, a window register which is currently used is W7, its value is inputted to a signal 14, and one of four instructions 12a-12d, i.e., 12b is an instruction which switches a register window to W7. A control means 11a outputs the value W0 of the signal 14 to a signal 13a since the instruction 12a is not the instruction for switching the register window, but a control means 11b outputs the signal 13a to W7 since the instruction 12b is the switching instruction. Consequently, the instruction, and register window signals W0, W7, W7, and W7 are fetched by instruction fetching means 10a-10d to know for which register window the respective instructions are executed at the stage of the fetch, so that the four instructions are executed in parallel.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a function of switching registers according to instructions.

0002

2. Description of the Related Art In a conventional information processing apparatus having a reduced instruction set architecture, instructions have a fixed length of 32 bits and operations are performed only between registers. Also, eight register windows W7, W6, . ．． , W0, and uses any one register window. Each register window consists of 32 32-bit registers: 8 global registers, 8 local registers, 8 input registers, and 8 output registers. Global registers are common to all register windows. The register window is arranged clockwise in a ring shape such as W7, W6, . ．． , W0, but the output register is the same as the input register of the register window on the right. For example, the output register of register window W0 and the input register of register window W7 are common. When calling the procedure, execute the save instruction and switch the register window to be used to the register window on the right. Similarly, when returning from a procedure,
Execute the restore command and switch to the register window on the left. Also, save/restore
The instruction adds data between registers in the register window before switching, and writes the result to the register window after switching.

[0003] Now, suppose that we start using the register window W7. If the save instruction is executed seven times without executing any restore instructions, register window W0 will be used, but the contents of the input registers and local registers in register window W7 must be saved to the stack area of memory. It disappears. This state is called overflow. This is because, as mentioned above, the output register of register window W0 and the input register of register window W7 are common, and writing to the output register of register window W0 does not destroy the contents of the input register of register window W7. This is to make it happen. When an overflow exception occurs, the CPU shifts to exception processing and saves the contents of the input register and local register in the register window W7 to the stack area of the memory by executing software.

[0004] After overflow exception handling is completed,
Restore 7 times without executing any save commands
When the instruction is executed, the register window W7 is used, but the contents of the register window W7 must be restored from the stack area of the memory. This state is called underflow. When an underflow exception occurs, the CPU moves to exception processing, and the contents of the input register and local register of the register window W7 are fetched from the stack area of the memory by executing software.

[0005]

A conventional information processing apparatus specifies one register window currently in use. Therefore, the instruction following the save/restore instruction can only be executed after the save/restore instruction is executed. save/restore command and sa
It is possible to execute multiple instructions in parallel between the ve/restore instruction, but for the reasons mentioned above, the save/restore instruction
Instructions before and after the tore instruction cannot be executed in parallel.

[0006] Also, the underflow of the window register
When an overflow occurs, the CPU enters exception handling, and executes software to save the register window value to the memory stack area and restore the register window value from the memory stack area. . Therefore, during this exception handling, the CPU cannot execute the next instruction.

[0007] The present invention solves the above problems, and
Provided is an information processing device that can execute multiple instructions including ve/restore instructions in parallel, and can prevent window register overflow and underflow from occurring. The purpose is to

[0008]

[Means for Solving the Problems] In order to solve the above problems, an information processing device of the present invention includes a plurality of register windows, has one or more types of switching instructions for switching the register windows, and has a plurality of instructions inputted. The number of the register window that is being used at the time when all the instructions that were input before the input of the plurality of instructions have finished execution is input, the switching instruction and type are detected, and the number is used for each of the plurality of instructions. The apparatus includes a plurality of control means for generating register window numbers, and an instruction fetch means for fetching the register window number and the instruction generated by the control means.

Further, the information processing device of the present invention includes a plurality of register windows storing stack pointers, an auxiliary register group consisting of a plurality of registers and temporarily holding the values of the register windows, and a register window storing the register windows. a memory for saving values, a first storage means for holding the window number of the register window, and overflow and underflow of the register window.
A second window that holds the window number that causes the flow's exception.
a first data transfer means for transferring data from the register window to the auxiliary register group and generating a stack pointer; and a first data transfer means for transferring data from the auxiliary register group to the memory. and a third data transfer means for transferring data from the memory to the register window, and is used as an instruction to switch the register window when calling a procedure. It includes an instruction A and an instruction B used when returning from the procedure, and when the instruction A is executed twice, the second
When instruction A is executed in a state where the register window is switched to the register window having the window number (for example, W0) held in the storage means, the first data transfer means is held in the second storage means. window number (W0
) transfers all or part of the contents of the register window (W7) and the stack pointer that are switched when instruction A is executed to the auxiliary register group, and then executes instruction A.
When executed, the second data transfer means transfers the value (W0) of the second storage means to the window to be switched when executing instruction A using the window number (W0) held in the second storage means. number (W7), and controls the second data transfer means to transfer the contents of the auxiliary register group to the memory using the stack pointer stored in the auxiliary register group, and executes instruction B. If instruction B is executed in such a state that when executed twice, the register window is switched to the register window with the window number held in the second storage means (for example, W7).
The first data transfer means reads the value of the register window (W6) using the window number (W6) held in the first storage means and transfers the stack pointer to the third data transfer means. The third data transfer means transfers all or part of the contents of the register window (W7) of the window number (W7) held in the second storage means from the memory to the register window (W7).
) and further execute instruction B, the third data transfer means transfers the value (W7) of the second storage means to the window number (W7) held in the second storage means. Window number (W0
).

0010

[Operation] With the above configuration, the control means receives the number of the register window in use at the time when all the previously input instructions have finished executing, receives a plurality of instructions, and selects the switching instruction and type. The instruction fetch means detects and generates a register window number to be used for each of the plurality of instructions, and the instruction fetch means fetches the register window number and the instruction generated by the control means, thereby identifying which register window at the fetch stage. It is possible to know which instruction to execute for a register window, and to execute instructions before and after an instruction to switch register windows in parallel in multiple register windows.

Furthermore, if the first instruction A is executed at a point where the register window W0 corresponding to the window number (for example, W0) held in the second storage means is executed when the instruction A is executed twice, When the second instruction A is executed, all or part of the contents of the register window W7 and the stack pointer are transferred to the auxiliary register group, and when the second instruction A is executed, the second
rewrites the value W0 of the storage means to the window number W7 that changes when the second instruction A is executed, and at the same time transfers the contents of the auxiliary register group to the memory,
Furthermore, when executing instruction B for the first time at a point where the register window W7 of the window number (for example, W7) held in the second storage means is selected when instruction B is executed twice, the first Using the window number W6 held in the second storage means, all or part of the register window W7 with the window number W7 held in the second storage means is transferred from the saved memory to the register window W7. , when the second instruction B is executed, the value W7 in the second storage means is rewritten to the window number W0 which is changed when the second instruction B is executed. In this way, by processing the saving/restoring of register window values using dedicated hardware, the processing can be performed in parallel with the execution of instructions and at high speed, and as a result, overflow and underflow of the register window can be avoided.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The information processing device according to the first embodiment of the present invention includes:
It is an information processing device that fetches/decodes four instructions from a single instruction stream within one cycle and executes the instructions in parallel as much as possible. The instructions have a fixed length, the operations use a reduced instruction set architecture that defines only operations between registers, and eight register windows are provided. Furthermore, since the configuration of the register window and its control have been explained in the section of the prior art, their explanation will be omitted here.

FIG. 1 shows a block diagram of an information processing apparatus according to a first embodiment of the present invention. In FIG. 1, 15 is an instruction stream, 12a, 12b, 12c, and 12d are four instructions fetched from the instruction stream 15, and 13
a, 13b, 13c, 13d, 14 are register window selection signals; 10a, 10b, 10c, 10d are instruction fetch means for fetching instructions and register window selection signals; 11a, 11b, 11c, 11d are register window selection signals and instructions This is a control means that receives as input and outputs a register window selection signal.

The operation of the information processing apparatus in the first embodiment configured as described above will be explained below. In the following, a case will be described in which four instructions including a save instruction are fetched from the instruction stream 15 and executed in parallel. Also, the register window currently in use is W0,
It is assumed that no overflow occurs even if the save instruction is executed. Assume now that instruction 12b is a save instruction, four instructions 12a, 12b, 12c, and 12d are executed using different arithmetic units (not shown), and there is no conflict in the registers used.

First, the control means 11a inputs the number W0 of the register window currently in use from the register window selection signal 14, and at the same time inputs the instruction 12a.Since the instruction 12a is not a save/restore instruction, the control means 11a inputs the register window selection signal 13a. The value of the register window selection signal 14 is output to. Next, the control means 11b inputs the register window selection signal 13a and at the same time inputs the instruction 12b, and since the instruction 12b is a save instruction, sa is selected in the register window W0 indicated by the register window selection signal 13a.
The number W7 of the register window to be switched by executing the ve instruction is output to the register window selection signal 13b. Further, the control means 11c inputs the register window selection signal 13b, and at the same time inputs the instruction 12c. Since the instruction 12c is not a save/restore instruction, it outputs the value W7 of the register window selection signal 13b as the register window selection signal 13c. Finally, the control means 11d inputs the register window selection signal 13c, simultaneously inputs the instruction 12d, and inputs the instruction 12d.
Since 2d is not a save/restore instruction, the value W7 of the register window selection signal 13c is output to the register window selection signal 13d as the value of the register window selection signal 14 when fetching the next four instructions.

With the above operation, the instruction fetch means 10
instructions 12a, 12b for a, 10b, 10c, 10d
, 12c, 12d and the register window numbers W0, W7, W7, W7 to be referenced by the respective instructions are fetched. Therefore, four instruction fetch means 10
When executing instructions stored in a, 10b, 10c, and 10d, it is determined which register window each instruction should refer to, and as mentioned above, each of the four instructions uses a different arithmetic unit. However, since there is no conflict in the registers used, the four instructions are executed in parallel. Here, using the register window number W7 stored in the instruction fetch means 10b when the save instruction is executed, the values of the two registers in the register window W0 are added and written in the register window W7.

As explained above, the information processing apparatus in the first embodiment has the advantage of switching register windows.
Multiple instructions including ave/restore instructions can be executed in parallel. Although this embodiment shows an information processing device that executes four instructions in parallel, save/restore operations can also be performed using the same method in information processing devices that execute five or more instructions in parallel.
It becomes possible to execute multiple instructions in parallel. Also,
In this embodiment, the instruction and the register window selection signal output from the i-th control means are input to the i-th instruction fetch means, but the instruction and the register window selection signal input to the i-th control means are ,i
A similar effect can be obtained by inputting the instruction to the second instruction fetch means. Furthermore, the control means 11a, 11b, 11c are
A signal indicating that an ave/restore command has been detected is output, and the control means 11d generates a register window selection signal using these three signals.
c generates a register window selection signal using the signals output from the control means 11a and 11b, and
It is also easily possible for b to generate the register window selection signal using the signal output from the control means 11a.

The information processing apparatus according to the second embodiment of the present invention includes eight register windows. The configuration of the register window and its control have been explained in the section of the prior art, so their explanation will be omitted here.

FIG. 2 shows a block diagram of an information processing apparatus according to a second embodiment of the present invention. In Figure 2, 200
is a window register consisting of eight register windows, 201 is a first storage means that holds the window number of the current register window, and 202 is a window number that holds the register window overflow and underflow exceptions. second storage means for holding, 20
3 to 209, 223, 224 are data buses, 210
is an auxiliary register group, 211 is a memory for saving the value of the register window, and 212 is a first memory for transferring the value of the register window 200 to the auxiliary register group 210.
data transfer means 213 is an auxiliary register group 210
214 is a third data transfer means that transfers the value of the memory 211 to the register window 200;
219, 225, 226 are address buses, 220, 2
21 is a stack pointer, and 222 is a CPU.

The operation of the information processing apparatus in the second embodiment configured as described above will be explained below. In addition,
It is assumed that the stack pointer for saving the register window to the memory 211 has been written to the output register. Now, assume that you start using the register window W7. In a conventional information processing device, an overflow exception occurs in the register window W0. In this embodiment, the value of the second storage means 202 is assumed to be W0.

[0021] Now, the value W0 of the second storage means 202 can be saved/restored several times without rewriting it.
Assume that after executing an instruction, a save instruction is executed and the window is switched to the register window W1. Here again s
When the ave instruction is executed, the register window W0 stored in the second storage means 202 is switched to, and in the conventional information processing apparatus, an overflow exception occurs in the register window W0. Then, the first data transfer means 212 transfers the value of the first storage means 201 and the second storage means 202 from the data buses 204 and 205.
reads and compares the values of , and if the save instruction is executed one more time, it is detected that the value of the first storage means 201 matches the value W0 of the second storage means 202, and the instruction to use the register window W1 is executed. In parallel with the execution of
is used to output an address to the address bus 219 and begin to transfer the values of the input register and local register of the register window W7 and the stack pointer stored in the output register of the register window W7 to the read auxiliary register group 210. Auxiliary register group 21
When the save instruction is executed again after the transfer to 0 is completed, the second data transfer means 213 transfers the value of the first storage means 201 and the second storage means from the data buses 204 and 205. 202 is read out and compared, it is detected that they match, the value of the second storage means 202 is rewritten to W7, and the second data transfer means is written in parallel with the execution of the instruction using the register window W0. 213 uses the stack pointer stored in the auxiliary register group 210 to output an address to the address bus 217 and outputs the value of the auxiliary register group 210 (memory 2 in the previous save instruction).
11) starts to be transferred to the memory 211. In the above manner, overflow of the register window W7 can be avoided.

Next, the operation for avoiding underflow of the register window will be described. Following the above operation, the second
After executing the save/restore command several times without rewriting the value W7 of the storage means 202, the restore
Assume that the store instruction is executed and the register window W6 is displayed. Restore again here
When the instruction is executed, the register window W7 stored in the second storage means 202 is switched to.
Generates a flow exception. Then, the third data transfer means 214 and the first data transfer means 212 read the value W6 of the first storage means 201 and the value W7 of the second storage means 202 from the data buses 204 and 205. By comparison, if the restore command is executed one more time, the value of the first storage means 201 will be changed to the value of the second storage means 202.
The first data transfer means 212 outputs an address to the address bus 219 using the value W6 of the first storage means 201, and the address is stored in the input register of the register window W6. The third data transfer means 214 reads the stack pointer and transfers it to the third data transfer means 214, and in parallel with the execution of the instruction using the register window W6, the third data transfer means 214 transfers the address to the address buses 218 and 219. Output and store in memory 211
The input register and local register values of register window W7 that were transferred to register window W
Start transferring to 7. Here, the address output to the address bus 218 is generated using a stack pointer, and the address output to the address bus 219 is generated using the value W7 of the second storage means 202. After completing the transfer to register window W7, restore
When the command is executed, the third data transfer means 214 rewrites the value of the second storage means 202 to W0. After the transfer to this register window W7 is completed, restore
If the e instruction is executed, no underflow will occur.

As explained above, the information processing device in the second embodiment uses dedicated hardware to process the saving/restoring of the values in the register window, so that the processing can be performed in parallel with the execution of instructions and at high speed. As a result, underflow and overflow of the window register can be avoided. Also, the value of the register window is saved in parallel with an instruction that uses the register window (for example, W1) two registers before the register window (for example, W7) that should be saved to memory, but by providing a group of auxiliary registers, Register window to be saved to memory (
For example, the value of the register window can be saved to memory only after switching to the previous register window (for example, W0) from W7).

The memory described in the second embodiment may be a storage device that the CPU can access by executing an instruction, such as a cache memory built into a microprocessor or a main memory external to the microprocessor. is an example.

[0025]

As described above, according to the present invention, in an information processing apparatus having a plurality of register windows, sav
When multiple instructions including the e/restore instruction are fetched, it is known which register window each instruction should use.
Multiple instructions including instructions can be executed in parallel.

Furthermore, by processing the saving of register window values using dedicated hardware, processing can be performed in parallel with the execution of instructions and at high speed.
It is possible to avoid the occurrence of a flow, and it is possible to save to the memory only after switching to the register window immediately before the register window to be saved to the memory. Then, by processing the return of data from memory to the register window using dedicated hardware,
Can be processed in parallel with instruction execution and at high speed, resto
The re instruction makes it possible to avoid underflow, speed up processing, and has great practical value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing device that can execute a plurality of instructions in parallel, including a save/restore instruction for switching register windows, according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an information processing device according to a second embodiment of the present invention that eliminates register window underflow and can execute the next instruction in parallel with overflow exception processing.

[Explanation of symbols]

Claims (2)

[Claims] 1. A device comprising a plurality of register windows, having one or more types of switching instructions for switching the register windows, in which a plurality of instructions are input, and execution of all instructions input before the input of the plurality of instructions is completed. a plurality of control means for detecting the switching instruction and type, and generating a register window number to be used for each of the plurality of instructions; An information processing device comprising: an instruction fetch unit that fetches the generated register window number and the instruction. 2. A plurality of register windows storing stack pointers, a group of auxiliary registers consisting of a plurality of registers and temporarily holding values of the register windows, and a memory for saving the values of the register windows. a first storage means for holding a window number of the register window; a second storage means for holding a window number for generating an overflow and underflow exception of the register window; first data transfer means for transferring data from the register window to the auxiliary register group and generating a stack pointer;
a second data transfer means for transferring data from the auxiliary register group to the memory; and a third data transfer means for transferring data from the memory to the register window; The instruction to switch the register window includes an instruction A used when calling a procedure and an instruction B used when returning from the procedure, and when the instruction A is executed twice, the instruction is retained in the second storage means. When the instruction A is executed in such a state that the register window is switched to the register window of the window number held in the second storage means, the first data transfer means switches when the instruction A is executed with the window number held in the second storage means. Transferring all or part of the contents of the register window and the stack pointer to the auxiliary register group, and further executing instruction A,
The second data transfer means rewrites the value of the second storage means to the window number that is changed when instruction A is executed using the window number held in the second storage means, and transfers the second data to the window number that changes when instruction A is executed. The data transfer means controls to transfer the contents of the auxiliary register group to the memory using the stack pointer stored in the auxiliary register group, and when the instruction B is executed twice, the contents are retained in the second storage means. When instruction B is executed in a state where the register window is switched to the register window of the window number, the first data transfer means reads the value of the register window using the window number held in the first storage means. The stack pointer is transferred to the third data transfer means, and the third data transfer means stores the contents of all or part of the register window of the window number held in the second storage means in the memory. When the third data transfer means transfers the data to the register window and further executes instruction B, the third data transfer means transfers the
An information processing apparatus characterized in that the information processing apparatus is configured to execute control for rewriting the value of the storage means to a window number that changes when instruction B is executed using the window number held in the second storage means.