JPS6360952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data conversion device that performs preprocessing for encoding to obtain an efficient code when transmitting or storing data, and an inverse conversion device that obtains original data from the converted data. It is related to the device.

2. Description of the Related Art In image transmission such as television and facsimile, or image storage such as character pattern memory and image information files, data is encoded for the purpose of shortening transmission time and storage capacity. An image is divided into a large number of small areas called pixels, and image information is composed of a set of numerical data corresponding to the color and density of each pixel. As is well known, such original image information contains a lot of redundancy, so the redundancy can be reduced by using the statistical properties of image information, which is a collection of a large number of numerical data. It is possible to reduce the amount of data and represent the image information without damaging the content of the image information. This is so-called data compression, in which the original image information is converted into a data-compressed code through encoding, transmitted or stored in the form of this code, and this code is decoded into the original image information by a decoding device. displayed as an image.

By the way, in signals such as television and facsimile, which are generated by scanning images line-sequentially, similar data with a fixed scanning period (for example, the period of the horizontal synchronization signal or vertical synchronization signal in the case of a television video signal) Columns are generated sequentially. Furthermore, in the rows (or columns) of data expressed in a two-dimensional matrix, such as character patterns, data columns (or rows) with similar content are often adjacent to each other, and these data columns are sequentially taken in a specific direction. If you do this, you will be able to obtain similar data at regular intervals. For data such as this, where similar data sequences are generated sequentially at regular intervals, if the predicted value of the data is obtained by a simple logical operation from data that was known before the data, this predicted value Since there is a high probability that the value matches the actual value of the data, data processing called predictive conversion is performed. Predictive conversion is performed by inputting a predicted value and an actual value of the data, performing a predetermined logical operation, and using the result as the converted value of the data. Data consisting of this converted value has less redundancy than the original data, so for example, run-length encoding (run-length encoding)
For many encoding methods such as length coding, it is more efficient to encode transformed data than to encode the original data as is, so predictive transformation is performed as pre-processing for encoding. In addition, the predictively converted converted data can be easily converted back to the original data by a predetermined logical operation corresponding to the logical operation at the time of conversion. The present invention relates to a device that performs such predictive transformation and inverse transformation.

Figure 1 is a coordinate diagram showing the interrelationship of data involved in predictive conversion, where the horizontal axis is the main scanning direction;
It is assumed that the vertical axis is the sub-scanning direction, and scanning is performed line-sequentially from the upper left to the lower right. It is assumed that one rectangular section surrounded by a dotted line in the figure represents one pixel, and the characters written in each pixel represent the numerical data of that pixel. In this example, already known pixel data A, B, C, and D are used to predict pixel data X.
If the predicted value for data X is expressed as X^, then X^=g(A, B, C, D)...(1). Here, g represents a predetermined logical operation.

The converted value Y of pixel data X is Y=h(X^,X) (2), where h represents a predetermined logical operation different from g. If the calculations shown in equations (1) and (2) are performed on all pixels while maintaining the positional relationship as shown in Figure 1,
The entire image is predictively transformed.

On the other hand, in the case of inverse transformation as well, for example, when inversely transforming the transformation data Y shown in FIG. Obtain X^ from 1), and from X^ and Y, obtain X=p(X^, Y)...(3). Here, p is a predetermined logical operation, and if the logical operation h is determined, the logical operation p is also determined. Formulas (1), (2) and formulas (1), (3) are combined into Y=(A, B, C, D, X)...(4) X=q
(A, B, C, D, Y)... can be expressed as (5). By the way, logical operations for predictive transformation and inverse transformation are determined according to the characteristics of the data. For example, if the image is binary black and white, white is the logical value "0",
If black is represented by the logical value “1”, equation (1) becomes X^
=A・(B+)+B・(+D)……(6),
Equation (2) is Y=X^X...(7), Equation (3) is X=X^Y...
(8) becomes. However, in formulas (6), (7), and (8), . represents logical product, + represents logical sum, and represents exclusive logical sum. If the predicted value X^
When matches the actual value X, Y becomes "0" according to equation (7). If the prediction of equation (6) is appropriate for the nature of the original data, the predicted value X^ and the actual value
The probability that "0" becomes "0" is significantly increased, and the converted data has many "0"s, making it possible to encode the data with high efficiency.

Figure 2 is a connection diagram showing an example of a conversion calculation circuit.
This is a logic circuit that performs calculations of equations (6) and (7). 21 is an inverter, 22, 23, 24 are OR gates, 2
5 and 26 are AND gates, and 27 is an exclusive OR gate. Data A shown in Figure 1,
If B, C, D, and X are respectively input to the terminals shown in FIG.
The output of gate 2 is X^ as shown in equation (6), and gate 2
7, the conversion output Y can be obtained by equation (7). In Figure 2, if one input of gate 27 is set to Y instead of X, the output of gate 27 is
becomes. That is, the circuit shown in FIG. 2 can also be used as a predictive inverse transform calculation circuit.

If the image has colors and/or halftones, data representing each pixel (for example, A, B,
C, D, X...) are expressed as binary numbers of 2 bits or more. In this case, g, h, and p in formulas (1) to (3) are respectively X^=1/2(A+B)+1/4(D-C)...(9) Y=X-X^...( 10) Let X=Y+X^...(11). Figure 3 is a connection diagram showing another example of the conversion calculation circuit. When the data of each pixel is expressed as a 3-bit binary number, the circuit performs calculations of equations (9), (10), and (11). FIG. 3a shows a conversion calculation circuit for calculating equations (9) and (10), and FIG. 3b shows an inverse conversion calculation circuit for calculating equations (9) and (11). In the figure, 30, 31, and 32 are each 4
33 is a 5-bit full adder,
301, 302, 303, 304, 305, 30
6 and 307 are inverters, respectively. Each of the full adders 30 to 33 has a carry input terminal (indicated by CI in the figure). When used for addition, a logic "L" signal is applied to this terminal, and when used for subtraction, a logic "H" signal is applied to this terminal. The fact that it is necessary to add a signal and invert the logic of each bit of the binary number representing the subtracted number (that is, create the complement of the subtracted number for 2 ⁿ -1) is the same as the usage of a general full adder. , therefore the output of the full adder 30 is (A+
B), and the output of the full adder 31 becomes (D-C). Furthermore, multiplication by 1/2 or 1/4 in binary numbers only requires a shift of 1 or 2 bits, so the output of full adder 30 is shifted by 1 bit, and the output of full adder 31 is shifted by 2 bits. It is clear that if the signals are input to the signal input terminals I ₁ and I ₂ of the full adder 32, the output of the full adder 32 will be X^ shown in equation (9). In FIG. 3a, the full adder 33 performs the calculation of equation (10) to obtain the converted value Y, and in FIG. 3b, the full adder 33 performs the calculation of equation (11) to obtain the inverse conversion. We are getting the value X.

Inferring from the relative positions of pixels A, B, C, D, and It is easy to understand that this would make highly efficient encoding possible.

By the way, since equations (9), (10), and (11) only involve multiplication by powers of 2, the circuit in Figure 3 does not need to have a special multiplier, but in general, conversion The arithmetic circuit and inverse conversion arithmetic circuit may need to have a multiplier/divider. Also, input data A, B, C,
If the total number of bits of D and A circuit and an inverse conversion calculation circuit can be configured.

Now, for example, the points in time at which data C, B, D, ... A, X are obtained by scanning as shown in FIG. must be input at the same time, and all pixels of one image must be successively supplied as the pixel X to be converted, and the pixels at the relative positions shown in FIG. 1 must be successively supplied to this pixel X.

Figure 4 is a block diagram showing an example of a conventional predictive conversion device, in which image data consisting of N pixels per scanning line is input one pixel at a time, and the corresponding conversion data is output one pixel at a time. It is a device that does In the figure, 40 is a conversion calculation circuit, which represents the entire circuit shown in FIG. 2 or 3 a, and 41, 4
Delay circuits 2 and 43 each delay input data by one data amount, and 44 a delay circuit that delays input data by (N-1) data. For example, if one pixel data is represented by n bits, 41,4
2 and 43 are parallel circuits each having n shift registers of one stage, and 44 is a parallel circuit of n shift registers having (N-1) stages. The scanning method shown in FIG. 1 and the delay circuits 41, 42, 4 shown in FIG.
3 and 44 together, the conversion calculation circuit 40
It is clear that data A, B, C, D, and X are input at the same time.

FIG. 5 is a block diagram showing an example of a predictive inverse transform device corresponding to FIG. 4, in which 50 is an inverse transform calculation circuit;
51, 52, and 53 are delay circuits that each delay input data by one data amount, and 54 is (N-1).
These delay circuits are delay circuits 41, 42, 43 and 44 that delay by the amount of data.
are configured identically. The pixel data that has already been inversely transformed is 1 data, (N-1) data,
The data are delayed by N data and (N+1) data and input as A, D, B, and C to the inverse conversion circuit 50 together with the converted data Y, and the inversely converted data X is output.

In addition, in predictive conversion and inverse conversion, data belonging to the first scanning line of an image and data X at both ends of each scanning line correspond to data A, B, C, and D having the positional relationship shown in Figure 1. In some cases, some of the data to be used does not actually exist, but in this case the same data values can be assumed in both the predictive and inverse transforms. For example, in a black and white binary image, pixels that do not actually exist may be assumed to have a white level, and the corresponding data value may be controlled to be "0".

The above is an explanation of conventional predictive conversion devices and predictive inverse conversion devices. In these conventional devices, the data of each pixel of an image is serially input one data at a time, and the corresponding output data is sequentially input one data at a time. I'm starting to get it. Therefore, an operation step is required to serially input and output all data one data at a time, and if the amount of data such as images is very large, it will take a considerable amount of processing time even if the operation speed is increased. Become. Further, in such a circuit, even though data originally has a parallel structure, it is required to serially rearrange the data for processing. For example, since a character pattern is originally a two-dimensional matrix of binary data, it is possible to handle a plurality of rows or columns in parallel. On the other hand, some printers that read and print character patterns have a wire dot or ink jet printing section and can print multiple lines at once. However, when character patterns are encoded by predictive conversion, conventional devices
Since this inverse conversion is performed serially line by line, the inversely converted data must be temporarily stored in memory and printed when it reaches the plurality of lines.

Similar inconveniences occur with modern facsimile machines. In recent facsimile devices, multiple light receiving elements and electrostatic recording heads are arranged in a direction perpendicular to the scanning line direction, and by mechanically moving this arrangement in the scanning line direction, data for multiple scanning lines can be processed in parallel. There are some that improve the overall scanning speed by reading and recording. When performing predictive conversion or inverse conversion with such a facsimile device, it is necessary to install a memory for multiple scanning lines after the image reading section and input data sequentially to the predictive conversion circuit one scanning line at a time, or to input the data into the predictive conversion circuit sequentially one scanning line at a time. A memory for a plurality of scanning lines must be provided in front of the circuit to temporarily store the output data from the predictive inverse transform circuit.

However, if predictive transformation and predictive inverse transformation can be performed in parallel on multiple data streams, the above-mentioned parallel data can be It can be processed as is, and the number of operation steps required for data conversion and inverse conversion processing can be significantly reduced, and processing time can be shortened. This leads to faster data processing devices such as printers and facsimile machines. Furthermore, the memory for storing data for multiple rows or multiple scanning lines as described above is not required, and the apparatus can be simplified.

This invention was made based on the above circumstances, and an object thereof is to provide means for performing predictive transformation and inverse transformation in parallel.

Embodiments of the invention will be described below with reference to the drawings. FIG. 6 is a block diagram showing an embodiment of the specific invention in this application. 61,6 in the figure
2, 63, and 64 are predictive conversion calculation circuits, respectively;
For example, each corresponds to the entire circuit shown in FIG. 2 or 3a. That is, the embodiment shown in FIG. 6 shows a case where four predictive conversion calculation circuits 61 to 64 are used to perform predictive conversion calculations on four data strings in parallel. Let N be the number of data in each data string. 600 is a delay circuit 60 for one data
a delay circuit for N-1 data, which is connected in series with 9 and delays the input data by N data (that is, one scanning line); 601, 602, 603, 60;
Delay circuits 4, 605, 607, 608, 609, and 610 each delay input data by one data. If the four scanning lines, that is, the scanning line numbers are j, (j+1), (j+2), (j+3), then these four scanning lines are scanned all at once, and j
The data from scanning lines No., (j+1), (j+2), and (j+3) are shown as L ₁ , L 2 , and L ₂ , respectively in FIG.
It is input to the input terminals shown as L ₃ and L ₄ , and when this simultaneous scanning is completed, the next one is (j+4), (j+5),
The four scanning lines (j+6) and (j+7) are scanned at the same time, and the data from the (j+4) scanning line is sent to terminal _L1 , and the data from the (j+5) scanning line is sent to terminal L. ₂ , ... are input respectively. Therefore _, data D _{1 ,} B ₁ , C _{1 corresponding} to data _{A 1} , It is clear that data B ₁ is obtained by further delaying in the delay circuit 601, and data C ₁ is obtained by further delaying in the delay circuit 602. Furthermore, data _{D 2 , B 2 ,} C ₂ corresponding to data A ₂ , All data to be input is fed in parallel. Therefore, the converted data
Y ₁ , Y ₂ , Y ₃ , Y ₄ are the output terminals l ₁ , l ₂ ,
Output from l ₃ and l ₄ in parallel.

FIG. 7 is a diagram showing the delay relationship between data in the circuit of FIG. 6, and the alpha-abbet symbol at the left end of the diagram is a signal on the conductor wire to which the alpha-abbet symbol is attached in FIG. 6. As these signals, the number of data in each data string arriving at each operation step is expressed as a numerical value from 1 to N.
The numerical value 0 in the figure is invalid data outside the data string, but represents the first and last data of each data string, and data necessary for predictive conversion of the first data string. The value of this invalid data is a predetermined specific value, and the delay circuits 600, 601, . . . , 610 are constituted by shift registers, and the contents of these shift registers are reset to represent the specific value. 7th
In the example shown in the figure, the shift registers 601 to 610 have been reset to this specific value, and the circuit operation starts from the point in time when the shift register 600 stores the data string immediately before the four data strings to be converted. is represented.

As is clear from Figure 1, data D is data X
Therefore, for example, in response to X ₂ where the data at input terminal L ₂ is delayed by 1 data by the delay circuit 605, the data from input terminal L ₁ is directly transferred to D _{2 .} becomes. Therefore, the converted data Y ₁ to output to the output terminals l ₁ to _{l 4
Y4} is the converted value of the original data input to the input terminals _L1 to _L2 one data before. Further, as already explained, data X ₄ obtained by delaying the input of terminal L ₄ by one data becomes input γ of delay circuit 600, and supplies data D ₁ , B ₁ , C ₁ for the next data string.
As shown in Fig. 7, the circuit of Fig. 6 requires only one invalid data 0;
1) Parallel predictive conversion of 4 data strings consisting of N data is completed in 1) operation steps.

FIG. 8 is a block diagram showing another embodiment of the present invention, in which the same reference numerals as in FIG. 6 indicate the same parts, and 85
is a predictive conversion calculation circuit, and as is clear from a comparison with FIG. 6, predictive conversion calculation circuits 61, 62,
It has a function that combines 63 and 64 functions. However, depending on the configuration of the predictive conversion calculation circuit, the circuit 85 may be more complex than the four circuits 61. For example, when the data of each pixel is a 1-bit signal,
If the circuit 61 is constituted by a ROM, it will be a small ROM with 5 input bits and 1 output bit, but the circuit 85 will be a large capacity ROM with 14 input bits and 4 output bits.

Although the circuit of FIG. 6 can be used as a parallel predictive conversion device, it cannot be used as a parallel predictive inverse conversion device. The reason for this is that even in the case of predictive inverse transformation, for example, the predictive transformation calculation circuit 63 uses the formula
(1) (Equation (6) or Equation (9) are specific examples of Equation (1)) must be performed to calculate X ₃ , but at this point, the predictive conversion calculation circuit 62 The data corresponding to C ₃ has already been inversely transformed, but the data corresponding to B ₃ is processed in the predictive conversion calculation circuit 63.
This is data that is inversely transformed at the same time as the operation of X ₃ ,
Since the data corresponding to D ₃ is inversely transformed with a delay of one data, the data required as input to the predictive transformation calculation circuit 63 is not yet prepared at the time of need. If parallel predictive inverse transformation cannot be performed in response to parallel predictive transformation, the aforementioned effects of speeding up processing and reducing unnecessary memory will be reduced.

Other inventions filed concurrently with this application were made in view of the above circumstances, and their purpose is to provide a device capable of parallel predictive inverse transformation, and in particular, to provide a device that is composed of the same parts and can be easily changed in connection. Therefore, it is an object of the present invention to provide a device that can be used both as a parallel predictive conversion device and as a parallel predictive inverse conversion device.

FIG. 9 is a block diagram showing another embodiment of the invention of this application, in which the same reference numerals as in FIG. 6 indicate the same or corresponding parts and they operate in the same way.
Further, 900 is a delay circuit corresponding to the delay circuit 600 in FIG.
1) Give a delay for the data. Also 901,90
2,903,904,905,906,907,
Delay circuits 908, 909, 910, 911, and 912 each provide a delay of one data.
The original data input from input terminals L ₁ to _{L 4} is the 6th
As in the case of the figure, the predictive conversion data output from the output terminals l ₁ to _{l 4} is the same as in the case of Fig. 6, but
Between L ₁ and L ₁ , between L ₂ and L ₂ , between L ₃ and L ₃ , and between L ₄ and
A delay circuit for 3 data is inserted between l ₄ , and the data input to L ₁ , L ₂ , L ₃ , and L ₄ at the same time is predictively converted and is delayed by 3 data at the same time.
The outputs are output from l ₁ , l ₂ , l ₃ , and l ₄ , but this delay circuit outputs all three data to the circuit 61 and outputs one data to the input side to the circuit 62. 2
The data portion is on the output side, 2 data portions are on the input side and output side for circuit 63, and 3 data portions are on the input side and output side for circuit 64.
Since all of the data is inserted into the input side, data processing is performed in the order of circuits 61, 62, 63, and 64 with a delay of one data. In this way, data processing is performed with a delay of one data point at a time, so
For example, the data from terminal L ₁ is passed directly to circuit 6.
1 can be input as data X ₁ , and can be input to circuit 62 as data D ₂ . In this point,
In the circuit of FIG. 6, the data from the terminal _L1 can be directly input to the circuit 62 as data _D2 , but the difference is that the data must be input to the circuit 61 through the delay circuit 603. This is advantageous when this circuit is used as a predictive inverse transform device, as will be explained in a later section. As described above, the circuit in FIG. 9 is similar to the circuit in FIG. 6, except that in circuits 61, 62, 63, and 64, data processing is performed with a delay of one data in the above circuit order. It is clear that in operation a predictive transformation is performed. However, if data from the j-th, (j+4)-th, etc. scanning lines are input to terminal _L1 , then the terminal
Data from the (j+3)th, (j+7)th, ... scanning lines are input to _L4 , so this (j+
3) When the data input from the (j+4)th scanning line is delayed by (N-1) data by the delay circuit 900, the data from the (j+4)th scanning line is delayed by N-(N-
This is equivalent to a delay of one data amount determined by 1)=1.

FIG. 10 is a diagram showing the delay relationship between data in the circuit of FIG. 9. Using the same display method as FIG. 7, each signal line in FIG. It shows what data is coming.

FIG. 11 shows an example in which a circuit having the same function as the circuit shown in FIG. 9 is configured using a single predictive conversion calculation circuit 110, and the four predictive conversion calculation circuits 61 to 64 in FIG. The configuration is the same as that of the circuit in FIG. 9 except that it is replaced with the circuit 110 of FIG.
It works the same way.

Next, FIG. 12 is a block diagram showing another embodiment of the invention of this application, and represents an example of the circuit configuration of a predictive inverse transform device. In FIG. 12, the same reference numerals as in FIG. 9 indicate the same or corresponding parts, and they operate in the same way. Further, 121, 122, 123, and 124 are predictive inverse transform calculation circuits, which are similar to the predictive conversion calculation circuits 61, 62, 63, and 64 in FIG. 9, only that the connection points between data X and data Y are exchanged. belongs to. Circuits 121, 122, 123, 12
Since data processing is performed with a delay of one data in the order of 4, the output data X ₁ of the circuit 121 can be directly input to the circuit 122 as data D ₂ , and _the output data It can be easily understood that it can be inputted to the circuit 123 as D ₃ and that predictive inverse transformation is performed in this way if considered in conjunction with the explanation regarding FIG.

FIG. 13 is a diagram showing the delay relationship between data in the circuit of FIG. 12. Using the same display method as in FIG. 10, each signal line in FIG. It shows what data is coming.
As is clear from FIG. 13, the converted data string for four periods having period N is inversely converted in parallel by (N+3) operation steps.

FIG. 14 shows an example in which a circuit having the same function as the circuit shown in FIG. 12 is configured using a single predictive inverse transform calculation circuit 140.
1 to 124 are simply replaced by a single circuit 140, and the circuit 140 is constituted by, for example, a ROM. Also, in Fig. 12, the inputs D ₂ , D ₃ , D ₄
is the same as X ₁ , X ₂ , and X ₃ , so the 14th
The figure prediction inverse transformation calculation circuit 140 has data D ₂ , D ₃ ,
There is no need to enter D ₄ .

In the above explanations of FIGS. 6 to 14, examples are given in which data for four cycles are predictively transformed and inversely transformed in parallel among a data group in which similar data is sequentially generated with N data as a cycle. As mentioned above, the number of data that can be processed in parallel is not limited to 4 cycles, but can be processed in any k cycles (k≧2
It is clear that data for (an integer of ) can be processed in parallel. In addition, in the above explanation, it is assumed that the correlation between each data is as shown in Fig. 1, and for the i-th data (X) in the j-th period, We have explained the case where the predicted value X^ of X is determined from the (i-1)th data (C) of the , (j
The present invention can also be applied to the case where up to the (i+q)th data (q≧1 integer) of the −1)th period is necessary to determine the predicted value X^. In such a case, the delay amount of the delay circuit 900 in FIG. 9, FIG. 11, FIG. 12, and FIG. And it is sufficient.

By the way, as is clear from the above explanation, the main parts of the predictive conversion device and the predictive inverse conversion device can be configured to be the same, so it is possible to switch a single device and use it as a predictive conversion device or a predictive inverse conversion device. can be designed. FIG. 15 is a block diagram showing a circuit that combines FIGS. 3a and 3b, in which the same reference numerals as in FIGS. It can be switched accordingly. For example, when the logic of the signal S is "L", the A side input of the selection circuit 150 is output, and the circuit in FIG. 15 becomes the circuit in FIG. 3a,
When the logic of the signal S is "H", the B side input of the selection circuit 150 is output, and the circuit of FIG. 15 is as shown in FIG. 3b.
The circuit becomes. However, if data X and data Y have different numbers of bits, it is sufficient to use only the necessary lower bits for the data with fewer bits. Further, in the circuit shown in FIG. 2 in which the data is only 1 bit, the predictive conversion calculation circuit and the predictive inverse conversion calculation circuit are the same, so there is no need for switching. Circuit 11 in Figure 11
0 and the circuit 140 in FIG. 14 are generally different in operation content, it is necessary to use the control signal S as a ROM address input and/or chip selection input to switch between the conversion operation and the inverse conversion operation. .

FIG. 16 is a block diagram showing another embodiment of the present invention, showing a device which can be used as both the predictive conversion device of FIG. 9 and the predictive inverse conversion device of FIG. 12 by switching.
In FIG. 16, the same reference numerals as in FIGS. 9 and 12 indicate the same or corresponding parts, and 161, 162, 1
63 and 164 are dual-purpose arithmetic circuits, 165,
166, 167, and 168 are selection circuits, respectively. The control signal S (not shown) is supplied to the arithmetic circuits 161 to 161.
164 and the selection circuits 165 to 168,
The circuit of FIG. 16 is switched to the connection shown in FIG. 9 or the connection shown in FIG. 12.

FIG. 17 is a block diagram showing still another embodiment of the present invention, showing a device which can be used as both the predictive conversion device of FIG. 1 and the predictive inverse conversion device of FIG. 14 by switching. In FIG. 17, the same symbols as in FIG. 11 and FIG. 14 indicate the same or corresponding parts, 170 is a dual-purpose arithmetic circuit, and 165, 166, 167, 168
is a selection circuit. A control signal S (not shown) is applied to arithmetic circuit 170 and selection circuits 165-168 to switch the circuit of FIG. 17 to the connection shown in FIG. 11 or to the connection shown in FIG.

As described above, when calculating the predicted value of each data, the present invention can be applied to the case where any data generated before the data is used, and an example thereof will be described below.
FIG. 18 is a coordinate diagram showing another example of the correlation of data related to predictive conversion, and is displayed in the same manner as in FIG. 1, but the difference from FIG. 1 is that data E is also This is also related to the predicted value of data X, and the equation corresponding to equation (1) is X^=g(A, B, C, D, E)...(12).
If the position of X is the i-th data of the j-th period, the position of E is (i+2) of the (j-1)th period.
This is the th data and q=2.

FIG. 19 is a block diagram showing another embodiment of the present invention. When the correlation of each data is as shown in FIG. 18, that is, when q=2, data for three cycles (k=3) is A predictive conversion device that performs predictive conversion in parallel is shown, where the same reference numerals as in FIG. 9 indicate parts having the same or similar functions, and a delay circuit 900 delays input data by (N-2) data and outputs the delayed data. Numerals 191, 192, and 193 are predictive conversion calculation circuits, and these circuits operate similarly to the prediction conversion calculation circuits 61 to 64, except that calculation of the predicted value X^ of the prediction conversion is performed using equation (12). q=2
Therefore, circuit 192 processes data with a delay of two data points from circuit 191, and circuit 193 processes data with a delay of two data points from circuit 191.
Data processing is performed with a delay of 2 data from that of circuit 92, and the input data of circuit 193 one cycle before is input to circuit 191 with a delay of (N-2) data, so that X ₁
is unchanged as E ₂ , X ₂ is unchanged as E ₃ ,
X ₃ is input as E ₁ after being delayed by (N-2) data, and predictive conversion is performed.

FIG. 20 is a diagram showing the delay relationship between data in the circuit of FIG. 19. Using the same display method as in FIG. 10, each signal line in FIG. It shows what data is coming.
As is clear from FIGS. 19 and 20, in order to complete the predictive conversion of m cycles of data string, N+(k-1)·q timings are required for the original data string length N. Steps are required. For this reason,
(k-1)q invalid data are added to each data string. In the example of FIG. 19, k=3 and q=2, and the predictive conversion is completed in (N+4) steps. Invalid data is represented by number 0 in FIG. The last data string among the data strings input in parallel is further delayed by (N-q) data and then supplies input data to the predictive conversion calculation circuit 191 . The output of the delay circuit 900 is (N-q) after all.
+(k-1)·q data is delayed. on the other hand,
Next, terminal L ₁ of the data string input in parallel
Since the data in the data string input to is invalid data, after N+(k-1)q steps, the data in the data string becomes data with the same number. Due to the difference between the two, the output data of the delay circuit 900 has a larger number in the data string by q than the input data of the terminal _L1 , and the predictive conversion calculation circuit 191 also receives data _E1 and data _X1 at the same time. Ru. In order to transform the circuit of FIG. 9 into the circuit of FIG. 11, the three circuits 191, 192, 193 of the circuit of FIG. 19 can be replaced with a single predictive conversion calculation circuit.

Now, if only the predictively converted data is to be output, it is not necessary to provide the delay circuits 907 to 912 in FIGS. 9, 11, and 19, so these delay circuits are not essential components of the invention. However, by giving such a delay and outputting the data of the same number (that is, the same value of i) in one cycle to the terminals l ₁ to l ₄ at the same timing,
From the outside of the predictive conversion device, data strings of all cycles are treated equally, so in the set of output converted data strings, the divisions for every k columns caused by the predictive conversion device are Therefore, a set of exactly the same converted data strings (excluding invalid data) can be obtained from predictive conversion devices with different values of k. Therefore, when performing predictive inverse transformation on a set of such transformed data sequences, the number m (m
≧2 integer) can be determined.

Further, for example, in the circuit of FIG. 9, the delay circuit 90
If 7 to 912 are omitted, the converted data output from the output terminals l ₁ to _{l 4} will have a delay of q data (q = 1 in the example in Figure 9), so such data will be encoded as is. , is input to the circuit in Figure 12 (k-m = 4 in the circuit in Figure 9 and the circuit in Figure 12) after decoding, etc., and is inversely transformed, the circuit in Figure 12 has a delay. Circuit 901~
It is clear that 906 can be omitted.

To summarize the features of the invention of this application, the first invention relates to FIGS. 6 and 8. (a) Similar data is sequentially generated at a constant period N (N is a positive integer). Divide a data group (for example, a television screen's worth of video signals) into data strings for each period (for example, the horizontal scanning period of a television video signal), and divide the data into k data strings whose generation order is adjacent to each other (k≧2). k data strings (in the case of FIG. 6, k = 4, for example, horizontal scanning number j, (j+1), (j+2), (j+3)) for a period of (integer)
4 data strings corresponding to the number) are output in parallel to the k input terminals L ₁ to _{L 4} of the first to kth,
One data string is applied to one input terminal from the above k data strings, and the generation order of the data strings corresponds to the numerical order of the input terminals (L ₁ is the j-th data string, L ₂ is (j+1) (numbered data string, ...) Each data string is input in the form of a data series, and the data of mutually corresponding numbers among the k data strings are inputted in synchronization with each other, and the above data are input to the same input terminal. One data string for every k data strings in the group (for example,
L ₁ has number j, number (j+k), number (j+2k),...
(b) for using the data string input to the k-th input terminal _L4 in a predictive conversion operation for the data string input to the first input terminal _L1 ; (c) Delay data string delay circuits ( ₆₀₉ and ₆₀₀ ); The present invention is characterized in that it includes input delay circuits (601 to 610) that provide a delay suitable for use in predictive conversion calculations for a data string whose generation order is one data point later than the data string, and (d) a predictive conversion calculation circuit. The second invention is, in addition to the above (a), (b), (c), and (d) regarding FIGS. 9, 11, and 19, (e) from each of the above input terminals. For each data string, the generation order is relatively q (a predetermined integer with q≧1, the 9th
The third invention is characterized by having relative delay circuits (901 to 906) that provide a relative delay so as to delay data by q=1 in the figure and q=2 in FIG. 19. Regarding FIGS. 12 and 14, (d) the predictive conversion calculation circuit in the second invention is changed to a predictive inverse conversion calculation circuit, and (c) the input delay circuit outputs the outputs X ₁ to X ₄ as shown in FIG. 12. The feature is that the output delay circuits (601 to 609) delay the output.

As described above, the present invention provides a device that can simultaneously perform predictive conversion and predictive inverse conversion on a plurality of data strings, and can also function as both a predictive conversion device and a predictive inverse conversion device by simple switching. Therefore, it is an effective means for speeding up operations and reducing the amount of memory in devices related to encoding for data transmission and storage.

[Brief explanation of drawings]

Fig. 1 is a coordinate diagram showing the interrelationship of data related to predictive conversion, Fig. 2 is a connection diagram showing an example of a conversion calculation circuit, Fig. 3 is a connection diagram showing another example of a conversion calculation circuit, and Fig. 4 is a block diagram showing an example of a conventional predictive conversion device, FIG. 5 is a block diagram showing an example of a predictive inverse conversion device corresponding to FIG. 4, and FIG.
7 is a diagram showing the delay relationship between data in the circuit of FIG. 6. FIG. 8 is a block diagram showing another embodiment of the first invention. FIG. 9 is a block diagram showing an embodiment of the second invention, FIG. 10 is a diagram showing the delay relationship between data in the circuit of FIG. 9, and FIG.
FIG. 12 is a block diagram showing another embodiment of the third invention; FIG.
3 is a diagram showing the delay relationship between data in the circuit of FIG. 12, FIG. 14 is a block diagram showing another embodiment of the third invention, and FIG. 15 is a diagram showing the delay relationship between data in the circuit of FIG.
16th block diagram showing a circuit that combines the circuits of
The figure is a block diagram showing still another embodiment of the third invention, FIG. 17 is a block diagram showing still another embodiment of the third invention, and FIG. 18 shows correlations of data related to predictive conversion. FIG. 19 is a block diagram showing still another embodiment of the second invention, and FIG. 20 is a diagram showing the delay relationship between data in the circuit of FIG. 19. 61, 62, 63, 64, 85, 110... Predictive conversion calculation circuit, 121, 122, 123, 12
4,140... Predictive inverse transformation calculation circuit, 600,9
00...Data string delay circuit, 601-610...
Input (output) delay circuit, 901-906...Relative delay circuit, _L1 - _L4 ...Input terminal, _l1 - _L4 ...Output terminal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A data group in which similar data is sequentially generated at a constant period N (N is a positive integer) is divided into data strings for each period, and k pieces ( k≧2
k data strings corresponding to a period of (an integer of Each data string is input in the form of a data series by matching the generation order and the numerical order of the input terminals, and data with corresponding numbers among the k data strings are input in synchronization with each other, and the same input The terminal includes data input means for inputting one data string for every k data strings in the data group, and data input means for inputting the data string to the k-th input terminal to the first input terminal. A data string delay circuit that delays the data string for use in a predictive conversion operation for a string, and a data string output from this data string delay circuit and each data string input from each of the above input terminals. The generation order is 1.
an input delay circuit that provides a delay suitable for use in a predictive conversion operation for a data string after the data, each data string from each of the input terminals, a data string output from the data string delay circuit, and the input delay circuit; A data conversion device comprising: a predictive conversion calculation circuit that receives each data string output from the input terminal and performs a predictive conversion calculation on each data string from each input terminal. 2 Divide a data group in which similar data is sequentially generated at a constant period N into data strings for each period, and output k data strings for k periods whose generation order is adjacent to each other in parallel. , the above k data strings are applied to the k input terminals from the first to the k-th, one data string per input terminal, and each data string is created by matching the generation order of the data strings with the numerical order of the input terminals. Data of corresponding numbers among the above k data strings are inputted in serial form and in synchronization with each other, and one input terminal is inputted to the same input terminal for each of the k data strings among the above data groups. A data input means for inputting a data string, and relative to each data string from each input terminal, q data strings (predetermined number of data strings with q≧1) whose generation order is relatively one data string later. a relative delay circuit that provides a relative delay so that the data is delayed by an integer), and a data string input from the k-th input terminal,
Through a relative delay circuit corresponding to the data string,
a data string delay circuit that further delays the data string input to the first input terminal for use in a predictive conversion operation; an output data string of the data string delay circuit; a data string from the first input terminal; an input delay circuit that gives each data string output from each relative delay circuit a delay suitable for use in a predictive conversion operation for the data string and a data string that is one data point later in generation order than the data string; A data string from the first input terminal, each data string output from each of the relative delay circuits, a data string output from the data string delay circuit, and each data string output from the input delay circuit are input. , a predictive conversion calculation circuit that performs a predictive conversion calculation on each data string from each of the input terminals. 3. From a data group in which the predictively converted data is generated in the form of a data series and each N pieces of data constitutes one data string, k data strings whose generation order is adjacent to each other are output in parallel, and the first The above k data strings are applied to one input terminal to the kth to k input terminals, and each data string is formed into a data series by making the generation order of the data strings correspond to the numerical order of the input terminals. data of mutually corresponding numbers in the k data strings are input in synchronization with each other, and one data string is input for each of the k data strings in the data group to the same input terminal. A data input means to be input, and a data string that is relatively one data string later in the generation order relative to each data string from each input terminal described above is relatively delayed by q data points. inputting a relative delay circuit that provides a delay, a data string from the first input terminal, and each data string output from each of the relative delay circuits, and performing a predictive inverse transformation operation on each of these data strings;
A predictive inverse transform calculation circuit that outputs each output data string obtained by predicting and inversely transforming each input data string; an output delay circuit that provides a delay suitable for use in a predictive inverse transform operation for a data string after the data and inputs the signal to the predictive inverse transform calculation circuit; A data string that is delayed and input to the predictive inverse transform calculation circuit for use in a predictive inverse transform operation on the data string that is input to the first input terminal. A data inversion device comprising a delay circuit.