JPS5721174A - Data converter and its inverter - Google Patents
Data converter and its inverterInfo
- Publication number
- JPS5721174A JPS5721174A JP9640680A JP9640680A JPS5721174A JP S5721174 A JPS5721174 A JP S5721174A JP 9640680 A JP9640680 A JP 9640680A JP 9640680 A JP9640680 A JP 9640680A JP S5721174 A JPS5721174 A JP S5721174A
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuits
- inputted
- input
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
- H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
- H04N1/413—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information
- H04N1/417—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information using predictive or differential encoding
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
- Image Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PURPOSE:To enable forecast conversion and inversion parallelly and to make the data processing high speed, by producing the data group separated into a given number of data train every period and subjecting forecast conversion to the data train adjacent to the data train in the production order. CONSTITUTION:Taking the number of data of input group as N, the N data' share is delayed with a data train delay circuit 600, and each input data is delayed by one data's share at input (output) delay circuits 601-610. Each data group is sequentially inputted to input terminals L1-L4 in the order of scanning of scanning line, the input data is inputted to forecase conversion operation circuits 62-64 and circuits 603, 604-609, 610 in series connection. The delayed output of the circuits 603-610 is inputted to circuits 62-64 inputted the data train after and before respectively, the output of the circuits 609, 610 is delayed for the data train's share at the circuit 600 and inputted to a forecast conversion and operation circuit 61 via the circuits 601-602. The operation of forecast conversion and inversion is executed in parallel at the circuits 61-64 for the output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9640680A JPS5721174A (en) | 1980-07-14 | 1980-07-14 | Data converter and its inverter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9640680A JPS5721174A (en) | 1980-07-14 | 1980-07-14 | Data converter and its inverter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5721174A true JPS5721174A (en) | 1982-02-03 |
JPS6360952B2 JPS6360952B2 (en) | 1988-11-25 |
Family
ID=14164077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9640680A Granted JPS5721174A (en) | 1980-07-14 | 1980-07-14 | Data converter and its inverter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5721174A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6251829A (en) * | 1985-08-30 | 1987-03-06 | Fujitsu Ltd | Parallel interpolation dpcm coding circuit |
JPS6251830A (en) * | 1985-08-30 | 1987-03-06 | Fujitsu Ltd | Parallel processing type plane forecasting circuit |
JPH01114181A (en) * | 1987-10-27 | 1989-05-02 | Canon Inc | Predictive coding system |
JPH01119185A (en) * | 1987-10-31 | 1989-05-11 | Canon Inc | Predictive coding system |
JPH03250995A (en) * | 1990-02-28 | 1991-11-08 | Nec Corp | Dpcm coder for picture signal |
JP2015144324A (en) * | 2013-12-27 | 2015-08-06 | 三菱電機株式会社 | Image encoder, image decoder, image encoding method and image decoding method |
-
1980
- 1980-07-14 JP JP9640680A patent/JPS5721174A/en active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6251829A (en) * | 1985-08-30 | 1987-03-06 | Fujitsu Ltd | Parallel interpolation dpcm coding circuit |
JPS6251830A (en) * | 1985-08-30 | 1987-03-06 | Fujitsu Ltd | Parallel processing type plane forecasting circuit |
JPH01114181A (en) * | 1987-10-27 | 1989-05-02 | Canon Inc | Predictive coding system |
JPH01119185A (en) * | 1987-10-31 | 1989-05-11 | Canon Inc | Predictive coding system |
JPH03250995A (en) * | 1990-02-28 | 1991-11-08 | Nec Corp | Dpcm coder for picture signal |
JP2015144324A (en) * | 2013-12-27 | 2015-08-06 | 三菱電機株式会社 | Image encoder, image decoder, image encoding method and image decoding method |
Also Published As
Publication number | Publication date |
---|---|
JPS6360952B2 (en) | 1988-11-25 |
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