JPS5660130A - Speed converting circuit - Google Patents
Speed converting circuitInfo
- Publication number
- JPS5660130A JPS5660130A JP13616079A JP13616079A JPS5660130A JP S5660130 A JPS5660130 A JP S5660130A JP 13616079 A JP13616079 A JP 13616079A JP 13616079 A JP13616079 A JP 13616079A JP S5660130 A JPS5660130 A JP S5660130A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay
- circuits
- output
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
- H04L5/24—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters
- H04L5/245—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters with a number of discharge tubes or semiconductor elements which successively connect the different channels to the transmission channels
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Manufacture And Refinement Of Metals (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To reduce a time lag with simple circuit constitution by making input- side digital multiplexing circuits differ in time lag and then by changing them over. CONSTITUTION:Input-side digital multiplexing circuit 11 is given different time lags by delay circuits 21 and 22 and connected to selecting circuit 23 respectively. When the multiplicity of circuit 11 is higher than that of output-side digital multiplexing circuit 12, circuit 23 selects circuit 11 with no time lag and sends its output to it according to a switching signal applied to terminal 25 and then sends the output to other circuits from the least-delay circuit successively by changing them over. Memory circuit 24 fetches the output by clock pulses, corresponding to circuit 12, applied to terminal 26 and outputs them onto circuit 12. When the multiplicity of circuit 11 is greater than that of circuit 12, on the other hand, circuit 23 changes the circuits over from the greatest-delay one in sequence. Thus, desired speed conversion can be performed. Consequently, delay is provided by only circuits 21 and 22 and the extremely simple circuit constitution can reduce the delay.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13616079A JPS5660130A (en) | 1979-10-22 | 1979-10-22 | Speed converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13616079A JPS5660130A (en) | 1979-10-22 | 1979-10-22 | Speed converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5660130A true JPS5660130A (en) | 1981-05-23 |
Family
ID=15168712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13616079A Pending JPS5660130A (en) | 1979-10-22 | 1979-10-22 | Speed converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5660130A (en) |
-
1979
- 1979-10-22 JP JP13616079A patent/JPS5660130A/en active Pending
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