JPS5654142A - Timing generating circuit - Google Patents

Timing generating circuit

Info

Publication number
JPS5654142A
JPS5654142A JP13013979A JP13013979A JPS5654142A JP S5654142 A JPS5654142 A JP S5654142A JP 13013979 A JP13013979 A JP 13013979A JP 13013979 A JP13013979 A JP 13013979A JP S5654142 A JPS5654142 A JP S5654142A
Authority
JP
Japan
Prior art keywords
signal
circuit
signal line
delay time
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13013979A
Other languages
Japanese (ja)
Inventor
Katsumi Fujinami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13013979A priority Critical patent/JPS5654142A/en
Publication of JPS5654142A publication Critical patent/JPS5654142A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

PURPOSE:To obtain a timing generating circuit of less hardware in the form of integrated circuit, by selectively using the signal having predetermined delay time among a plurality of clock signals produced in response to an input signal. CONSTITUTION:When an input signal is given to a poly-phase clock generating circuit 1 via a signal line 4, (n) sets of clock signals corresponding to it are output to n lines of signal lines 5. The n sets of clock signals are fed to a switching circuit 2, and one clock signal is output to a signal line 7 in response to the switching selection signal given via a signal line 6. At this stage, an arbitrary and comparatively large delay time is obtained. Further, the delay time is further finely adjusted at the delay circuit 3 at next stage. This circuit 3 is the combination of respective delay circuits with the delay control signal given via a signal line 8 and the clock signal obtaining required delay time by this is output on a signal line 9.
JP13013979A 1979-10-09 1979-10-09 Timing generating circuit Pending JPS5654142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13013979A JPS5654142A (en) 1979-10-09 1979-10-09 Timing generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13013979A JPS5654142A (en) 1979-10-09 1979-10-09 Timing generating circuit

Publications (1)

Publication Number Publication Date
JPS5654142A true JPS5654142A (en) 1981-05-14

Family

ID=15026886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13013979A Pending JPS5654142A (en) 1979-10-09 1979-10-09 Timing generating circuit

Country Status (1)

Country Link
JP (1) JPS5654142A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157116A (en) * 1984-12-28 1986-07-16 Nec Corp Decode counter
JP2010028342A (en) * 2008-07-17 2010-02-04 Sanyo Electric Co Ltd Dll circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157116A (en) * 1984-12-28 1986-07-16 Nec Corp Decode counter
JP2010028342A (en) * 2008-07-17 2010-02-04 Sanyo Electric Co Ltd Dll circuit

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