JPS5765030A - Switching signal generating device for stereo demodulation - Google Patents

Switching signal generating device for stereo demodulation

Info

Publication number
JPS5765030A
JPS5765030A JP14050780A JP14050780A JPS5765030A JP S5765030 A JPS5765030 A JP S5765030A JP 14050780 A JP14050780 A JP 14050780A JP 14050780 A JP14050780 A JP 14050780A JP S5765030 A JPS5765030 A JP S5765030A
Authority
JP
Japan
Prior art keywords
output
frequency
division
duty
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14050780A
Other languages
Japanese (ja)
Other versions
JPS6222490B2 (en
Inventor
Yoshimi Iso
Shigeki Inoue
Toshifumi Shibuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14050780A priority Critical patent/JPS5765030A/en
Priority to US06/236,536 priority patent/US4392020A/en
Priority to DE3107028A priority patent/DE3107028C2/en
Publication of JPS5765030A publication Critical patent/JPS5765030A/en
Publication of JPS6222490B2 publication Critical patent/JPS6222490B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/1646—Circuits adapted for the reception of stereophonic signals
    • H04B1/1653—Detection of the presence of stereo signals and pilot signal regeneration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE:To enable simple constitution with less number of circuit elements and to reduce dispersion in delay time, by confirming the phase relation of each frequency dividing output with logic circuits so that the relation is always as specified relation. CONSTITUTION:The output of a VCO in which the output frequency is a prescribed frequency, 228kHz, is inputted to a buffer 28 to input the output of the buffer 28 to a 1/6 frequency-divider consisting of T-FF21-23 and D-FF24, allowing to obtain two types of frequency-divided outputs different in the phase with 1/6 duty. The two types of frequency-division outputs are inputted to an RS latch 25 to output the 1/6 frequency division output in duty 50% from the latch 25. The output of the FF21 and the output of the FF24 are ANDed to obtain a 1/2 frequency-division output having different phase relation with 1/6 frequency-division output waveform with duty 50%. The 1/6 frequency-division output and the 1/2 frequency-division output being the output of the latch 25 are inputted to the D-FF26, 27 respectively to delay them by taking the frequency of the VCO output as clock, and synchronized 1/6 and 1/2 frequency division outputs are outputted for switching.
JP14050780A 1980-02-27 1980-10-09 Switching signal generating device for stereo demodulation Granted JPS5765030A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP14050780A JPS5765030A (en) 1980-10-09 1980-10-09 Switching signal generating device for stereo demodulation
US06/236,536 US4392020A (en) 1980-02-27 1981-02-20 Stereo demodulation system for an FM stereo broadcast receiver
DE3107028A DE3107028C2 (en) 1980-02-27 1981-02-25 Stereo demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14050780A JPS5765030A (en) 1980-10-09 1980-10-09 Switching signal generating device for stereo demodulation

Publications (2)

Publication Number Publication Date
JPS5765030A true JPS5765030A (en) 1982-04-20
JPS6222490B2 JPS6222490B2 (en) 1987-05-18

Family

ID=15270250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14050780A Granted JPS5765030A (en) 1980-02-27 1980-10-09 Switching signal generating device for stereo demodulation

Country Status (1)

Country Link
JP (1) JPS5765030A (en)

Also Published As

Publication number Publication date
JPS6222490B2 (en) 1987-05-18

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