JPS5466062A - Clock synchronous circuit - Google Patents

Clock synchronous circuit

Info

Publication number
JPS5466062A
JPS5466062A JP13250377A JP13250377A JPS5466062A JP S5466062 A JPS5466062 A JP S5466062A JP 13250377 A JP13250377 A JP 13250377A JP 13250377 A JP13250377 A JP 13250377A JP S5466062 A JPS5466062 A JP S5466062A
Authority
JP
Japan
Prior art keywords
circuit
exclusive
phase
output
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13250377A
Other languages
Japanese (ja)
Other versions
JPS5716544B2 (en
Inventor
Yoichi Saito
Izumi Horikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13250377A priority Critical patent/JPS5466062A/en
Publication of JPS5466062A publication Critical patent/JPS5466062A/en
Publication of JPS5716544B2 publication Critical patent/JPS5716544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain a simple and cheap circuit, by composing two exclusive-OR circuits of one discriminator, delay line, LPF, and voltage control oscillator. CONSTITUTION:Exclusive-OR circuit 22 phase-compared signals (d), (i) and (m) discriminated 20 and regenerated by output (regenerative clock) signal (C) of voltage control oscillator 16 with output signal (e) delayed 21 by T/2, thereby obtaining output waveforms (f), (j) and (n). Then, the 2nd phase comparison between the output signal of circuit 22, and regenerative clock signals (c), (h) and (l) having passed through delay line 21' with the same delay time as circuit 22 is done by exclusive OR circuit 22', thereby obtaining pulse strings (g), (k) and (o) whose duty ratios are 50%, more than 50%, and less than 50% when phases coincide, delay and advance. Next, those signals are integrated by LPF15 to obtain zero, positive and negative voltages and the phase of oscillator 16 is controlled corresponding to the positive and negative voltage, so that when phases synchronize, the system will become stable.
JP13250377A 1977-11-07 1977-11-07 Clock synchronous circuit Granted JPS5466062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13250377A JPS5466062A (en) 1977-11-07 1977-11-07 Clock synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13250377A JPS5466062A (en) 1977-11-07 1977-11-07 Clock synchronous circuit

Publications (2)

Publication Number Publication Date
JPS5466062A true JPS5466062A (en) 1979-05-28
JPS5716544B2 JPS5716544B2 (en) 1982-04-06

Family

ID=15082876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13250377A Granted JPS5466062A (en) 1977-11-07 1977-11-07 Clock synchronous circuit

Country Status (1)

Country Link
JP (1) JPS5466062A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH054500Y2 (en) * 1987-02-14 1993-02-04

Also Published As

Publication number Publication date
JPS5716544B2 (en) 1982-04-06

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