JPS5575363A - Timing extracting circuit - Google Patents

Timing extracting circuit

Info

Publication number
JPS5575363A
JPS5575363A JP14773378A JP14773378A JPS5575363A JP S5575363 A JPS5575363 A JP S5575363A JP 14773378 A JP14773378 A JP 14773378A JP 14773378 A JP14773378 A JP 14773378A JP S5575363 A JPS5575363 A JP S5575363A
Authority
JP
Japan
Prior art keywords
circuit
register
output
signal
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14773378A
Other languages
Japanese (ja)
Other versions
JPS6138663B2 (en
Inventor
Seijiro Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14773378A priority Critical patent/JPS5575363A/en
Publication of JPS5575363A publication Critical patent/JPS5575363A/en
Publication of JPS6138663B2 publication Critical patent/JPS6138663B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

PURPOSE:To reduce the jitter occurrence in an assured way by installing the register which memorizes the data immediately before the convension point of the bipolar signal exists and then carrting out the phase control at only the specific conversion point which is selected through the comparison of the contents of the register. CONSTITUTION:The phase is controlled based on the rise or fall conversion point information of the bipolar signal featuring the frame structure containing the duodecimal logic 1 and 0, and the timing signal synchronized with the bipolar signal is extracted. In such case, the bipolar signal sent from input terminal IN is applied to full-wave rectifier circuit 11 to be converted into the signal of the same polarity. This signal is applied to comparator circuit 2, and the pulse is generated at the conversion point when the pulse reply is detected in the output of circuit 11 to memorize 0 or 1 of the output pulse of circuit 12 in register 13. Then the comparison is given between the output of circuit 12 applied to logic circuit 14 and the value memorized in register 13 immediately before. And the control is given to digital phase lock loop circuit 10 only when the output of circuit 12 is 1 with the immediately preceding value of 0 respectively.
JP14773378A 1978-12-01 1978-12-01 Timing extracting circuit Granted JPS5575363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14773378A JPS5575363A (en) 1978-12-01 1978-12-01 Timing extracting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14773378A JPS5575363A (en) 1978-12-01 1978-12-01 Timing extracting circuit

Publications (2)

Publication Number Publication Date
JPS5575363A true JPS5575363A (en) 1980-06-06
JPS6138663B2 JPS6138663B2 (en) 1986-08-30

Family

ID=15436905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14773378A Granted JPS5575363A (en) 1978-12-01 1978-12-01 Timing extracting circuit

Country Status (1)

Country Link
JP (1) JPS5575363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117839A (en) * 1983-11-29 1985-06-25 Fujitsu Ltd Clock extracting system
EP0209306A2 (en) * 1985-07-09 1987-01-21 Nec Corporation Phase-locked clock regeneration circuit for digital transmission systems

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117839A (en) * 1983-11-29 1985-06-25 Fujitsu Ltd Clock extracting system
EP0209306A2 (en) * 1985-07-09 1987-01-21 Nec Corporation Phase-locked clock regeneration circuit for digital transmission systems

Also Published As

Publication number Publication date
JPS6138663B2 (en) 1986-08-30

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