JPS54122943A - Synchronizing unit - Google Patents
Synchronizing unitInfo
- Publication number
- JPS54122943A JPS54122943A JP2991278A JP2991278A JPS54122943A JP S54122943 A JPS54122943 A JP S54122943A JP 2991278 A JP2991278 A JP 2991278A JP 2991278 A JP2991278 A JP 2991278A JP S54122943 A JPS54122943 A JP S54122943A
- Authority
- JP
- Japan
- Prior art keywords
- hazard
- clock
- period
- time
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Information Transfer Systems (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE: To reduce the useless time of sampling, by using the synchronizing signal having longer period than the hazard rectifying time before sampling and using the clock having desired period after sampling.
CONSTITUTION: Two clock having short and long period are inputted to FF10, 11, and the period of clock inputted to FF10 is about 3/2 period of hazard convergence time. When the asynchronous signal A and T1 input are duplicated at (a), hazard is caused to Q1. The detection circuit 13 opens the AND gate 15 after the hazard of Q1 is set and the signal without hazard is inputted to the data terminal D2 of FF11. If hazard has timing continuous to the time point (b), when the trigger input of FF11 uses the clock of the same period, it coincides at time point (c). In this case, if a clock faster than that to T1 is inputted to T2, FF11 is set at (d), and useless time can be reduced by the time difference between (d) and (c) in comparison with the clock with the same period to T1 and T2.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2991278A JPS54122943A (en) | 1978-03-17 | 1978-03-17 | Synchronizing unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2991278A JPS54122943A (en) | 1978-03-17 | 1978-03-17 | Synchronizing unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54122943A true JPS54122943A (en) | 1979-09-22 |
JPS5731167B2 JPS5731167B2 (en) | 1982-07-02 |
Family
ID=12289192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2991278A Granted JPS54122943A (en) | 1978-03-17 | 1978-03-17 | Synchronizing unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54122943A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202515A (en) * | 1985-03-06 | 1986-09-08 | Hitachi Ltd | Synchronizing circuit for asynchronous signal |
JPH03257650A (en) * | 1990-03-08 | 1991-11-18 | Matsushita Electric Ind Co Ltd | Latch method for parallel digital signal |
-
1978
- 1978-03-17 JP JP2991278A patent/JPS54122943A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202515A (en) * | 1985-03-06 | 1986-09-08 | Hitachi Ltd | Synchronizing circuit for asynchronous signal |
JPH03257650A (en) * | 1990-03-08 | 1991-11-18 | Matsushita Electric Ind Co Ltd | Latch method for parallel digital signal |
Also Published As
Publication number | Publication date |
---|---|
JPS5731167B2 (en) | 1982-07-02 |
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