JPS57129525A - Two-way code converting system - Google Patents

Two-way code converting system

Info

Publication number
JPS57129525A
JPS57129525A JP1547681A JP1547681A JPS57129525A JP S57129525 A JPS57129525 A JP S57129525A JP 1547681 A JP1547681 A JP 1547681A JP 1547681 A JP1547681 A JP 1547681A JP S57129525 A JPS57129525 A JP S57129525A
Authority
JP
Japan
Prior art keywords
clock
pll circuit
phase
circuit
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1547681A
Other languages
Japanese (ja)
Inventor
Hirohisa Karibe
Masushi Ikezawa
Toshihiko Matsumura
Hirokazu Fukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1547681A priority Critical patent/JPS57129525A/en
Publication of JPS57129525A publication Critical patent/JPS57129525A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/02—Reversible analogue/digital converters

Abstract

PURPOSE:To realize the asynchronous action of two-way code conversion, by providing the 1st PLL circuit plus its subordinate 2nd PLL circuit. CONSTITUTION:The 2nd PLL circuit 25 receives clocks CLK1 and CLK2 of different phases which have a comparatively high frequency compared with the clock that is produced from a voltage control type oscillator within the 1st PLL circuit 24. Then one of these two clocks is selected through a clock selecting circuit 31 to be used as a clock CLK3. This clock CLK3 is divided by a frequency divider circuit 32 to produce a clock corresponding to a receiving synchronous signal 27, and the phase comparison is carried out through a phase comparator 30. The clock is consecutively used if the state of phase is satisfactory and then replaced with another clock if the state of phase becomes unsatisfactory.
JP1547681A 1981-02-04 1981-02-04 Two-way code converting system Pending JPS57129525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1547681A JPS57129525A (en) 1981-02-04 1981-02-04 Two-way code converting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1547681A JPS57129525A (en) 1981-02-04 1981-02-04 Two-way code converting system

Publications (1)

Publication Number Publication Date
JPS57129525A true JPS57129525A (en) 1982-08-11

Family

ID=11889846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1547681A Pending JPS57129525A (en) 1981-02-04 1981-02-04 Two-way code converting system

Country Status (1)

Country Link
JP (1) JPS57129525A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224121A (en) * 1986-03-25 1987-10-02 Sony Corp Digital-analog or analog-digital conversion integrated circuit
JPS6486617A (en) * 1987-09-28 1989-03-31 Matsushita Electric Ind Co Ltd Signal processing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224121A (en) * 1986-03-25 1987-10-02 Sony Corp Digital-analog or analog-digital conversion integrated circuit
JPS6486617A (en) * 1987-09-28 1989-03-31 Matsushita Electric Ind Co Ltd Signal processing circuit

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