JPS5824518Y2 - waveform shaper - Google Patents

Description

[Detailed explanation of the invention] (a) Technical field of the invention This invention converts an input signal with a constant repetition period into a waveform with a waveform ratio of 0.
．． This waveform shaper is capable of converting the input signal into a signal of 5, and can arbitrarily set the delay time for the input signal over approximately one period of the input signal.

(b) Prior Art A phase detection circuit for detecting a sine wave signal requires a reference signal synchronized with the signal under test as shown in FIG.

The conversion point P of this reference signal is 1/1 of the period T as shown in FIG.
It must be at 2.

Such a reference signal is generally obtained by taking a synchronization signal from an oscillator or the like used as a generation source of the signal under test, and applying this synchronization signal to a waveform shaper to obtain a target reference signal.

Such a synchronization signal uses a sine wave or a square wave with a different waveform ratio, and often does not match the phase of the signal under test.

In such cases, conventional waveform shapers adjust the waveform ratio using a monostaple circuit using a time constant of a capacitor and a resistor, or correct the delay time to match the phase.

(c) Problems with conventional technology Conventional waveform shapers require readjustment when the values of capacitors and resistors that determine the time constant change due to changes in ambient temperature, or when the frequency of the input signal to the waveform shaper changes. There is a problem that it may become.

(d) Purpose of the invention This invention uses a phase-locked loop to eliminate the need for readjustment as long as it is in the locked region of the phase-locked loop, and the waveform ratio can be adjusted to any arbitrary value for the input signal at the O05 level. The present invention provides a waveform shaper that can set a delay time.

(e) Example of implementation of the idea A block diagram of an embodiment based on this invention is shown in FIG. 2.

In FIG. 2, 1 is a phase detector, 2 is a low-pass filter, 3 is a voltage controlled oscillator, 4 is an N-ary counter, 50 to 59 are gate circuits, 6 is a switch, I is a flip-flop, 8 is a gate circuit, 9 is an N/binary counter, 10 is a binary circuit,
11 surrounded by a dotted line is a phase-locked loop composed of 1 to 59.

A phase detector 1 in a phase-locked loop 11 detects a phase difference between an input signal and a feedback signal from a gate circuit 50, which will be described later, and lowers the output of positive polarity or negative polarity so that the phases of both signals match. It is sent to a voltage controlled oscillator 3 via a band pass filter 2.

Next, FIG. 3 shows an example of waveforms at each part of the second circuit.

The input signal A to FIG. 2 is a square wave with period T as shown in FIG. 3A.

It is sufficient for the input signal A to have a waveform ratio of about 0.1 to 0.9.

If the human input signal is a sine wave, it can be converted to a square wave using a waveform conversion circuit.

3 shows the output waveform of the voltage controlled oscillator 3 whose phase is locked by the input signal A, and this output is added to the N-ary counter 4.

The N-ary counter 4 in FIG. 2 is an example of a decimal counter constituted by four binary circuits 41 to 44 (N210-f).

Figure 3 shows the output waveforms of the binary circuits 41 to 44, respectively, and when 100 signals from Figure 3 are added, one signal is output as shown in Figure 3.

When each output of the binary circuits 41 to 44 is connected as shown in FIG. 2 and applied to gate circuits 50 to 59, the gate circuit 50
59, the waveforms shown in FIG. 3 50-59 are obtained.

The waveforms 50 to 590 in Fig. 3 are the period T of Fig. 3 A, respectively.
It has a width of l/10 and a time delay of (1/10)T.

In FIG. 2, switch 6 is connected to the output of gate circuit 59. In FIG.

The gate circuit 59 is applied with the waveform marked with a circle in the hull of FIG.

By switching the switch 6, any one of the waveforms shown in FIGS. 50-59 can be applied to the flip-flop 7.

This is to determine the phase delay time from the input signal A, as shown in FIG.

In addition, in FIG. 2, the output of the gate circuit 50 is connected to the phase detector 1.
It is used as a return signal.

The waveform of FIG. 3 59 is added to the 7 lip-flop 7 of FIG. 2, and the waveform of FIG.
When the waveform of FIG. 59 is applied, the output of flip-flop 7 is at L level, and when the waveform of FIG. 3, 59 is applied, the output of flip-flop 7 becomes H level.

The gate circuit 8 receives the waveform shown in FIG. 3 (opening) and the waveform shown in FIG.

The output of gate circuit 8 is added to N/2 counter 9.

In the embodiment shown in FIG. 2, since the N-ary counter 4 is a decimal counter, the N/2-ary counter 9 becomes a 5-ary counter.

In FIG. 2, three binary circuits 91 to 93 constitute a quinary counter.

Therefore, when five signals shown in FIG.

The output of the N/binary counter 9 is applied to the binary circuit 10, resulting in the waveform shown in FIG.

The reason for using the N/binary counter 9 is as follows.

That is, when the N-ary counter 4 is used in the phase-locked loop 11, N signals as shown in FIG. 3 are obtained during the period T, so that the binary circuit 10 is
This is to obtain an output with a waveform ratio of 1:1 as shown in FIG.

That is, in order to improve the reproducibility of the output signal N, the N-ary counter 4, the N/2-ary counter 9, the binary circuit 10, and the flip-flop 7 are reset before being operated.

As an application example of this invention, if N-ary counters 4 are connected in cascade, the phase can be precisely adjusted.

For example, if three decimal counters are connected in series, the drinking phase can be adjusted with an accuracy of 1/1000 of one cycle of the input signal A.

In this case, a 500-base counter that generates one pulse every time 500 pulses are counted is used as the N/binary counter 9.

(f) Effect of the idea This idea has the following effects.

(a) Since a phase-locked loop is used, even if the input signal fluctuates slightly, if the phase-locked loop is in the locked region, an output responsive to the fluctuation will be obtained, and the phase angle of the output signal with respect to the input signal will not change. No need to readjust.

(b) Even if the frequency of the input signal changes, the waveform ratio remains 0.
5, a highly stable signal can be obtained as a reference signal for phase detection.

(c) By switching switch 6, the waveform ratio becomes 0.
．． A signal having an arbitrary delay time with respect to the input signal can be obtained with a choice of 5.

[Brief explanation of drawings]

Fig. 1 is a diagram of the relationship between the signal under test and the reference signal of the phase detection circuit, Fig. 2 is the constituent countries of the embodiment according to this invention, and Fig. 3 is the waveform of each part of the second part. Detector, 2...Low pass filter, 3...Voltage controlled oscillator, 4...N
Advance counter, 50-59... Gate circuit, 6.
...Switch, 7...Flip-flop, 8...Gate circuit, 9...N quaternary counter, 10...Binary circuit, 11... ...
- Phase locked loop, 41-44...Binary circuit, 91-93...Binary circuit.

Claims (1)

[Claims for Utility Model Registration] A phase-locked loop having an N-ary counter in its feedback circuit, and a phase-locked loop that combines the outputs of the N-ary counter and has a width of N with respect to the period T of the input signal, and (1/N ) a first gate circuit that takes out N signals with delays of T; a flip-flop that receives the output of the first gate circuit; and a first gate circuit that inputs the output of the flip-flop and the output of the phase lock loop. 2 gate circuit, a hexadecimal counter that receives the output of the second gate circuit as input, and a binary circuit that receives the output of the V binary counter as input; The oscillation frequency of the voltage controlled oscillator in the lock loop is locked to the input signal, and the first gate circuit output is selected and applied to the flip-flop to keep the waveform ratio at 0.5. On the other hand, N) A waveform shaper whose main feature is to set the delay time in T steps.