SU1450109A1 - Phase autotuning device - Google Patents

Abstract

The invention relates to radio engineering, the purpose of the invention. The elimination of the ambiguity of the phase of the output signal. The device contains a tunable rr-1, a phase detector 2 with a saw-tooth, a multiplier 3 with a controllable gain factor, a low-pass filter 4, a driver 7 pulses, a trigger 8, driver 9 pulses, a transition through zero, el-t I 10, el-t or 11, threshold el-12 and meter 15 beat frequency. Target is achieved by introducing an AND-10 and OR-11, providing a capture mode with an unambiguous steady-state phase, which excludes the possibility of establishing phase errors corresponding to 2 voltage drops from maximum to minimum across the x-phase detector. The device in p. 2 f-ly is characterized by the introduction of threshold element 12 and meter 15, which functions as a synchrometer indicator, which controls the value of the multiplier 3 gain coefficient, sets it to be high in transient mode and equal to one. in synchronous operation mode of the device. 1 z..p.f-ly, 1 ill. with s o)

Description

The invention relates to radio engineering, to synchronization systems and is an improvement of the invention by ed. No. 985946.

The purpose of the invention is to eliminate the ambiguity of the phase of the output signal-3 nala.

The drawing shows a structural .electrical diagram of the device phase-10 voy auto-frequency.

The device comprises a tunable generator 1, a phase detector 2 with a sawtooth characteristic, a multiplier 3 made with a controlled 15 gain, a low-pass filter (low-pass filter) 4, a differentiating circuit 5, a rectifier 6, a pulse shaper 7, a trigger 8, a pulse shaper 9 voltage transition through zero (FNP), element AND .10, element OR. 11, threshold element

12, a pulse expander 13, a low-pass filter 14 and a beat frequency meter 15. The beating frequency meter 15 is formed by 25 differentiating circuit 5, rectifier 6, pulse expander 13 and low-pass filter 14.

The device operates as follows, 30

In the tracking mode, the slowly changing voltage at the output of the phase detector 2 does not lead to the appearance of pulses at the outputs of the 7-pulse shaper and the low-pass filter 9 and, accordingly, trigger 8 does not change its state. In this case, the device operates as a conventional PLL system; the signal from the output of the phase detector 2 passes through 40 multiplier 3 without change and then through the low-pass filter 4 it enters the control input of the tunable generator 1.

In the absence of synchronism at high- 45. Phase detector 2 appears-. beating voltage, as a result of which, at the output of the shaper 7 pulses, pulses appear, the repetition rate of which is equal to the difference frequency allocated by the differentiating circuit 5 and rectifier 6, and at the output of the FSF 9 pulses with a frequency twice as high. The pulse from the output of the shaper 7 of the impulses changes the state of the trigger 8, while for the duration of its action the pulse arising in the FNP. 9 is blocked (the interlock circuit is shown by the dotted line). After changing the state of trigger 8, the signal arriving at the input of the multiplier from the output of phase detector 2 is inverted, amplified by a factor of K, and fed to the input of the low-pass filter 4. The reverse state of the trigger 8 is pulsed from the output of the low-pass filter 9, which passes through the OR 11 element to the second input of trigger 8. As a result of such work of the circuit elements, an asymmetrical voltage is formed at the input of the low-pass filter 4 with a pronounced, constant component of the voltage, which allows to expand the capture band and increase the speed of the device.

To ensure a capture mode with a unambiguous steady-state phase, the AND 10 and OR 11 elements are used. If the trigger 8 is in state 1, the pulse from the output of the pulse shaper 7 passes through the AND 10, OR 11 elements to the second input of the trigger 8, setting it to the required state 0. This eliminates the possibility of establishing phase errors corresponding to the characteristic of the phase detector 2 by the voltage drop from the maximum value to the minimum value. .

To ensure a wide grip band and reduce the time of synchronization, the gain K of the inverter included in the multiplier 3 is selected to be large.

The meter 15 actually performs the functions of an indicator of synchronism, which controls the magnitude of the gain of the multiplier 3, setting it high in transition mode and equal to unity in the synchronous mode of the device.

Claims (2)

Claim 1. The device phase-locked loop for autosw. No. 985946, characterized in that, in order to eliminate the ambiguity of the phase of the output signal, an AND element and an OR element are introduced into it, moreover, the zero-crossing pulse shaper is connected in series with the trigger through the OR element, the inputs of the And element are connected to the output of the triggers | hera and pulse shaper, respectively, and the output of the AND element is connected to another input of the OR element. 2. The device according to π. 1, characterized in that the multiplier is made with a controlled gain, and between the output of the phase detector with a sawtooth characteristic and the input of the gain control of the multiplier are connected in series a beat frequency meter and a specific element,