SU1252940A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and provides an increase in the spectral frequency of the output signal. The digital frequency synthesizer contains a reference oscillator 1, a frequency-phase detector (FFD) 2, two oscillators 3 and 4 current (GT), an OR 5 element, a low-pass filter 6, a controlled oscillator 7, a frequency divider 8 with a variable coefficient. division, integrator 9, sampling-storage device 10, pulse start generator 11, frequency divider 12 and pulse distributor 13 (PI). In the synchronism mode of the phase-locked loop of the frequency, the pulse from the reference generator 1 opens the first output of the FPD 2. Its output signal opens the GT 3. Under the action of the current it generates, the voltage at the output of the integrator 9 drops. The impulse with RI 13 closes the first output of the FFD 2, and through the element OR 5 it opens the GT 4. Its current raises the voltage at the output of the integrator 9 to the initial level. The position of the output pulses of the RI 13, which are feedback pulses of the phase locked loop in the synchronism mode, is rigidly connected with the pulses of the reference oscillator after a certain number of periods of the output oscillation of the frequency synthesizer, i.e. the phase shift remains constant. 2 Il. § (L dycod

Description

The invention relates to radio engineering and can be used to form a grid of frequencies in radio transmitting and receiving devices.

The purpose of the invention is to increase the spectral purity of the output signal.

Fig. 1 shows the structure of the digital frequency synthesizer; Fig. 2 shows an embodiment of a pulse starter for the start of a cycle.

The digital frequency synthesizer contains a reference oscillator 1, a frequency-phase detector (PFD) 2, the first 3 and second 4 current generators, the element OR 5, a low-pass filter 6 (LPF), a controlled oscillator 7, a frequency divider 8 with a variable division factor (DPKD) ), integrator 9, sampling-storage device 10, pulse start generator 11. cycle divider 12 frequency, pulse distributor 13. In this case, the driver 11 of the pulse of the beginning of the cycle contains the first 14, second 15, third 16, fourth 17 D-triggers, the first 18 and the second 19 AND-NOT elements.

Digital frequency synthesizer works as follows.

I

The pulse repetition frequency from the output of the controlled oscillator 7 f in the PDCD 8 is divided into a repetition frequency equal to the signal frequency of the reference oscillator 1 f. The DPD 8 output pulse, the duration of which in the general case may not be associated with a certain number of output oscillation periods of the controlled generator 7, starts the driver 11 with its leading edge. Then, using the pulses coming from the output of the controlled generator 7, the clock input of the former 11 in It produces a pulse whose duration is equal to a certain number of periods of input pulses. The impulse from the output of the imaging unit 11 sets the frequency divider 12 to the initial state, which, after the termination of the specified pulse, begins to divide the frequency of the pulses arriving at its counting input from the output of the controlled oscillator 7 by the number M and generates at its output a pulse sequence with the repetition frequency f / M

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The pulse from the output of the imaging unit 11 also triggers the distributor of 13 pulses, which, under the action of the pulses from the output of the frequency divider 12, coming to its clock input, generates pulses at its outputs that are equal in duration to a certain number of periods of the output pulses of the frequency divider 12,

 Oh but separated by time.

In the synchronism mode of the phase-locked loop of a frequency, a pulse from the output of the reference generator 1 opens the first with its leading edge

 5 PFD 2 output, the output of which, in turn, opens the first current generator 3, which is a current source, under the action of which current the output voltage

integrator 9 drops. A pulse from the first output of the distributor of 13 pulses with its front edge closes the first output of the FPD 2, and through the element OR 5 opens the second generator 4 of the current, which is the element of the current retraction, under the action of which the voltage at the output of the integrator 9 rises to the original level.

Thus, this data,

the duration of which is chosen greater than the size of the dead zone of the FFD 2, shifts the working point of the discriminatory characteristic of the FFD 2 for the period of its action. Therefore, the position of the output pulses of the distributor 13 pulses, repeating at a frequency f and which are feedback pulses of the phase-locking loop in loop synchronization mode, is rigidly connected to the pulses of the reference oscillator after a certain number of periods of the output oscillation of the frequency synthesizer, and this number of periods does not vary in the output frequency range of the synthesizer, i.e. phase shift between the output oscillation of the digital synthesizer

The frequencies and oscillations of the reference oscillator in the output frequency range of the synthesizer remain constant.

The finally established voltage from the output of the integrator 9

during the action of the pulse from the second output of the distributor, 13 pulses are transmitted to the output of the sampling-storage device 10, from where

3

The LPF 6 is fed to the input of the frequency control of the controlled oscillator 7.

Thus, transients appearing at the output of integrator 9 due to the non-simultaneity of the currents of the first 3 and second 4 current generators are released from the input of the controlled generator 7, and therefore the level of the side components with the frequency of the reference generator 1 in the output spectrum oscillations of the frequency synthesizer are significantly reduced compared with the known synthesizer, while maintaining a high short-term frequency stability and the same frequency setting speed.

The shaper 11 operates as follows.

The DPKD 8 output pulse with its leading edge records a logical 1 from the D input of the first D-trigger 14 to its output. The first element AND-NOT 18 is opened and the output pulses of the controlled generator 7 are fed to the C inputs of the second 15 and fourth 17 D-flip-flops in the inversion. The first positive differential at the C input of the fourth D-flip-flop 17 writes a logical 1 to its output. Linking the second 15 and third 16 D-flip-flops and the second element NAND 19 after passing the third positive differential to the C input of the second D flip-flop 15 at the output of the second element NAND 19 generates a logic level O, which resets all D- Triggers into the state of logical O. As a result, at the output of the fourth D-flip-flop 17, a pulse is generated that is equal in duration to two periods of output pulses of the controlled oscillator 7.

The distributor 13 can be executed in the form of a shift register. Frequency divider 12 can be built on the basis of standard frequency divider chips with a preset of the initial state or reset to zero. The magnitude of the coefficient M is chosen from the consideration that the output pulse frequency of the frequency divider 12 is

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low enough for use in the distributor 13 pulses of cost-effective microcircuits and can be on the order of 10-50 depending on the frequency range of the synthesizer.

The integrator 9 can be built on the basis of an operational amplifier with a capacitor in the negative-to-feedback circuit or another principle.

Claims (1)

Invention Formula 5 A digital frequency synthesizer containing a series-connected reference oscillator, a frequency-phase detector and a first current generator connected in series 0 low-pass filter, controlled oscillator and frequency divider with inverted dividing ratio, serially connected element OR and second current generator, the output of which is combined with the output of the first current generator, the first input of the OR element connected to the second output of the frequency-phase detector characterized in that, for the purpose of 0 increases the spectral purity of the output signal, between the output of the frequency divider with a variable division factor and the second input of the frequency-phase detector are introduced after, coherently connected to the start-of-cycle pulse former, frequency divider and pulse distributor, and between the output of the first current generator and the lower filter input hour The one is entered in series by the integrator and the sample-storage device, the control input of which is connected to the second output of the pulse distributor, clock The second input of the pulse start generator is combined with the counting input of the frequency divider and connected to the output of the controlled oscillator, the output of the start cycle pulse generator Q is connected to the installation input of the pulse distributor, the output of which is also connected to the second input of the OR element.  From7 K1Zn13 Editor A. Kozoriz Compiled by Y. Kovalev Tehred L.Serdyukova Proofreader V.Sinitska Order 4631/57 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4