SU1713102A1 - Phase-lock loop - Google Patents

Description

The invention relates to radio engineering and communication technology and can be used in frequency-controlled auto-tuning systems with a wide tuning range, frequency synthesis systems.

The aim of the invention is to improve the noise immunity of the device.

Figure 1 shows the structural electrical circuit of the device; Fig. 2 is a circuit diagram representing an example of a specific implementation of the first and second low-pass filters and the adder of a phase locked loop device. /

The phase locked loop contains a tunable oscillator 1, a frequency divider 2, a phase detector 3, a reference signal source 4, a first low-pass filter (LPF) 5. pulse generator 6, a second low pass filter 7. an additional frequency divider 8, a capacitor 9, and an adder 10.

The device works as follows.

In the synchronous mode of operation of the device, the constant voltage from the output of the phase detector 3 through the first low-pass filter 5 and the adder 10 maintains the frequency of the adjustable oscillator 1C with an accuracy up to a phase equal to the frequency of the reference source. The pulse shaper 6 does not generate pulses, therefore blocks 8, 9, and 7 do not affect the operation of the device, in this case.

Serially connected blocks 6, 8, 9 and 7 affect the operation of the device only in transient mode. When a detuning in frequency occurs at the input of the phase detector 3, beats appear at its output, from which pulse generator 6 produces pulses with a beat frequency. The pulse sequence from the output of the pulse driver 6 is divided K times by an additional frequency divider 8 than

high noise immunity of the device is achieved. The presence of an additional divider 8 excludes the formation of an additional control voltage with single and t-multiple interferences vt fault x 1m K |.

After dividing the input frequency by K times the pulse from the output of the additional divider passes through capacitor 9 and goes to the second low-pass filter 7, the time constant of which is chosen sufficient to form a linearly varying search voltage.

Thus, in the presence of frequency detuning, an additional search voltage is applied to the control circuit of the tunable oscillator, providing entry into synchronism. Consequently, the band of the first low-pass filter 5 can be chosen rather narrow, and synchronization inspiration is provided by the formation of an additional search effect, while the ratio between the band of the first low-pass filter 5 and the search speed is chosen as for conventional search systems of automatic frequency control. The presence of an additional frequency divider 8 ensures the high noise immunity of the device.

Ph o rm aa and 3 o b te n A Phase-locked loop device containing connected sequentially adjustable oscillators, a frequency divider, a phase detector, whose other input is connected to a reference source, and a first low-pass filter, as well as a driver impulses and an adder connected to a control input of an adjustable oscillator, characterized in that, in order to improve noise immunity, connected in series between the impulse driver output and one adder input An additional frequency divider, a capacitor and a second low-pass filter, the input of the pulse generator is connected to the B1 input of the phase detector, and the output of the first low-pass filter is connected to another input of the adder.

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Claims (1)

Claim A phase locked loop device containing a series-tunable oscillator, a frequency divider, a phase detector, the other input of which is connected to a reference signal source, and a first low-pass filter, as well as a pulse shaper and an adder, connected to the input of the adjustable oscillator, characterized in that, in order to increase the noise immunity, an additional frequency divider connected in series between the output of the pulse shaper and one input of the adder Toty capacitor and a second low-pass filter, a pulse shaper input connected to the output. phase detector, and the output of the first low-pass filter is connected to another input of the adder. You*. fig 1