SU661842A1 - Phase-manipulated pseudo-random signal receiver - Google Patents

Description

the home of the delay tracking unit, the output of which is connected to the second input of the first multiplier, as well as the phase detector, which is output through a series-connected low-pass filter and controlled with a clock generator connected to the first input of the phase detector, the third and fourth multipliers, the second a synchronous detector, the first and second phase shifters, an additional low-pass filter and a controlled frequency divider, the output of which is the output of a clock generator through the first connected in series azovarshdatel, the second synchronous detector, the third multiply-5 gel and an additional low-pass filter is connected to the first input of the controlled frequency divider, the output of which is connected to the first input of the fourth multiplier, to the other end of the control unit and another to the third multiplier , while the output of the second multiplier is connected to another input of the second synchronous 25 detector and to the second input of the fourth multiplier, the output of which is connected to the second {mlm input of the phase-detector, with this The output of the controlled clock generator is connected to another input of the controlled frequency divider,.

FIG. 1 shows the structural electrical circuit of the device; in fig. 2 - timing diagrams, illustrating the principle of operation of the sync channel. .

Device for receiving phase-shifted pseudo-random signals

contains in series 40 the first multiplier 1, block 2, designed for phase self-tuning, synchronous detector 3, block 4, intended for tracking the delay, channel 5, intended for 45 extracting information, control block 6, delay element 7, the output of which is connected with the first input of the second multiplier 8, whose second input is connected to the input of the delay element 7 gn, the first input of the first multiplier i and another input of the synchronous detector 3, the output of which is connected to another input of channel 5, and the output power supply unit 6 is connected "

A block 4 input, the output of which is connected to the second inputs of the first multiplier 1, as well as a phase detector 9, which is drawn from the third line: a low-pass filter 10 and a controlled clock 60 generator 11 are connected to the first input of the Phase Detector 9, the third and fourth multipliers 12 and 13, the second synchronous detector 14, the first and second FF1zbvrava; teli l5 and 16, additional 65

A tel filter 17 and a controllable div (frequency 18 is 18, the output of the controlled clock oscillator 11 is connected through the first phase shifter 15, the second synchronous detector 14, the third multiplier 12 and the additional low-pass filter 17 to the first input of the controlled frequency divider 18 / whose output is connected to the first input of the fourth multiplier 13, another input of the control unit b and through the second phase shifter 16 to another input of the third multiplier 12, while the output of the second multiplier 8 is connected to another input of the Second synchronous detector 14 and the second input of the fourth multiplier 13, the output of which is connected to the second input of the phase detector 9, while the output of the controlled clock generator 11 is connected to another input of the controlled divider 18, the synchronization channel 19,

The device works as follows.

In synchronous mode B1: the total phase-manipulated signal is received by the binary pseudo-random sequence at the input of the device and in the first multiplier 1 is converted into a harmonic signal by multiplying with the reference binary signal coming from the output of block 4 and filtered by the unit of phase auto-tuning 2. in the synchronous detector 3 is converted into a binary sequence, since its second input receives a harmonic signal from the output of the phase locked loop 2. Dedicated binary The signal is fed to block 4 and. In channel 5 to highlight the information. The unit 4 for tracking the delay monitors the temporal position of the phase-shift keyed signal by determining the maximum mutual correlation of the received and reference signals. Channel 5 for extracting information, by comparing the received sequence with the reference signal, selects the information pulses that are sent to the erio first all. A signal about the presence or absence of synchronization from the second output of channel 5 to extract information is fed to the control unit 6

In the absence of synchronization, the control unit b connects the output of the synchronization channel 19 to the setup input of unit 4. At the same time, the pulses of the synchronization channel 19, which carry information about the temporal position of the received signal, return the receiving device to the synchronized position.

The operation of the synchronization channel 19 is implemented as follows.

Claims (1)

5 The signal from the input of the south device enters the device for selecting the clock frequency formed by the delay element 7 and the second multiplier 8. At the same time, the component of the phase-manipulated pseudo-random signal and the same signal shifted in time by half the clock frequency period contains the component clock frequency pseudo-random signal. Since the delayed pseudo-random signal manipulation causes the clock phase to be manipulated by, the phase of the selected clock frequency variation varies in accordance with the binary information premises. To remove this phase shift keying to obtain a harmonic signal. the signal from the output of the device for the selection of the clock frequency is fed to the fourth multiplier 13, to the second input of which a meander signal is fed corresponding to the information packets. The selected harmonic clock signal is filtered by the phase-locked clock frequency unit formed by sequentially turning on the phase detector 9, the filter 10 and the controlled clock generator 11 / whose output is connected to the second input of the phase detector 9. The filtered clock harmonic signal from the controlled clock output generator 11 through the first phase shifter 15 is fed to the input of the second synchronous detector 14, to the second input of which the FM clock signal comes from the output torogo multiplier 8. As a result, the output of the second synchronous detector 14 is released meander signal in accordance with information parcels. Thus, the meander signal is filtered in the following correlator, which includes the third multiplier 12, the additional low-pass filter 17, the controlled frequency divider 18, the second phase shifter 16. In this case, as a result of multiplying the selected information meander A meander signal of a controlled frequency divider 18, passing through the second phase shifter 16 to the second input of the third multiplier 12 and filtered with an additional filter 17, a voltage appears at the input of the latter, proportional to Noe value mutual correlation function of these signals. This voltage controls the division ratio. The frequency-controlled frequency is 18, so that the temporal mismatch between these signals tends to zero. This process is illustrated by the discriminatory characteristics of the phalan clock frequency control unit (see Fig. 2a) and the next correlator. torus (see fig. 2b). Suppose that is the initial moment of the detuning between the received and reference meander signals is equal to T. At the same time, at the output of the third multiplier 12, the voltage is equal to U, which changes the division ratio of the controlled frequency divider 18, which leads to a discrete change in the delay from T to tj and so on to T, until the voltage at the output of the third multiplier becomes zero ( or will be within the deadband). Subsequently, the phase-locked clock frequency unit monitors the phase of the clock frequency and at the expense of a constant division factor, and the phase of the square wave signal, maintaining the maximum mutual correlation between the received and reference square wave signals. Since the information meander is tied in time to the beginning of the pseudo-random sequence, the pulses from the output of divider 18 carry information about the temporal position of the pseudo-random sequence, which allows the receiving device as a whole to be in the synchronism position. The application of the proposed device allows to obtain the noise immunity of the following cracks. the same as that of the well-known, Thai as the bandwidth of the tracking correlator is many times smaller than the band of the phase-locked clock frequency block, which leads to an almost error-free removal of the manipulation of the signal by the frequency clock; At the same time, the use of a servo correlator for the temporal position of the information meander makes it possible with high accuracy to induce impulses in the code in the device for tracking the delay, which on average reduces the number of attempts to drive in until the correct result is achieved. In addition, this device is not affected by the Doppler shift of the clock frequency, which in the known device led to undesirable effects of a deviation of the driving pulse from the nominal value, because the transient process in the phase-locked loop when the phase jumps by 180 ° depends on the initial conditions that vary according to the Doppler shift of the clock frequency. Apparatus of the Invention A device for receiving phasomanipulated pseudo-random signals comprising successively