SU815962A1 - Device for receiving pseudorandom phase-manipulated signals - Google Patents

Description

(54) DEVICE TO RECEIVE Pseudo-incidental phase-shifting signals

a phase locked phase control unit and a synchronous detector, the second input of which is connected to the first input of the first multiplier, the second input of which is connected to the first input of the information extraction unit and the first output of the delay tracking unit, the first input of which is connected to the output of the synchronous detector and the second input of the unit information extraction, the output of which is connected to the first input of the control unit, the output of which is connected to the second input of the delay tracking unit, and the second input of the control unit is connected to the output Signalizer, the input of which is connected to the output of the differentiating unit, the input of which is connected to the output of the first low-pass filter, the input of which is connected to the output of the phase detector, the inputs of which are connected respectively to the outputs of the second multiplier and the clock generator, to the input of which is connected the output of the first low-pass filter , while the output of the delay element is connected to the first input of the second multiplier, the second input of which is connected to the input of the delay element, entered in series a frequency multiplier, a third multiplier, a second low-pass filter, a controlled oscillator, a mixer and a band-pass filter whose output is connected to the input of the delay element, the second output of the delay tracking unit and the first input of the first multiplier are connected respectively to the input of the frequency multiplier and the second mixer input , and the output of the second multiplier is connected to the second input of the third multiplier.

The drawing shows a structural electrical circuit of the proposed device.

The device contains the first multiplier 1, phase-locked loop (PLL) unit 2, synchronous detector 3, information extraction unit 4, delay tracking unit 5, control unit 6, signal conditioner 7, differentiation unit 8, first low-pass filter 9 (LPF) , phase detector 10, second multiplier 11, clock generator 12, delay element 13, frequency multiplier 14, third multiplier 15, second low frequency filter 16 (LPF), controlled oscillator 17, mixer 18 and band pass filter 19.

The device works as follows.

In the case of no synchronization, information extraction unit 4 permits control unit 6 to transmit pulses to the installation input of unit 5. In the signal spectrum of the multiplier, which together with delay element 13 is a signal convolution device, the FMN signal clock frequency and the doubled intermediate frequency 2 are most strongly distinguished. f .It is known that the dependence of the power of the first harmonic of the clock frequency on time

delays oscillate when the delay changes, and the oscillation frequency depends on the ratio f m / ftr p. At p 8 and the delay C fc.f / 2 (where K is the length of the pseudo-random sequence element) the clock frequency at the output of the second multiplier 11 corresponds to the global maximum. With n 7 the energy of the clock frequency with the same delay at the output of the multiplier is zero. With an instability of a ratio of 1 and n, there is a "floating content under the envelope, which naturally leads to a strong amplitude modulation of the selected clock frequency. The cause of this instability is the instability of the high-frequency oscillators of the receiver, the instability of the transmitter frequency, the Doppler shift, etc. THEN, the low-pass filter 9 and the clock generator 12. To eliminate this phenomenon and, consequently, increase the noise immunity of the device in the synchronization input mode, an additional interpolation circuit consisting of Connections to the ring multiplier 15, the LPF 16, a controlled oscillator 17, mixer 18, band pass filter 19 and a convolution unit - consisting of multiplier 11 and delay element 13. The reference signal for this PLL circuit is the frequency of the clock generator in block 5, multiplied by an even number of times. At the output of the second multiplier 11, there is always a doubled intermediate frequency 2 Fqi, in the presence of a signal at the input of the device. It is used for phase matching with the reference frequency in multiplier 15. As a result, the value of fpq becomes equal to a multiple of ff. Thus, the convolution device is fine tuned to the global maximum clock frequency. The further process of putting the device into synchronism does not differ from that of the known process. The information manipulation on the delay of code words formed by the SRP periods causes phase shift of the clock frequency, which does not affect the 21pc phase of the output of the second multiplier 11. Therefore, the setting of the convolution device does not violate, but the PLL circuit from phase detector 10, low-pass filter 9 and the clock generator 12 each time rebuilds the phase of the generator 12 on p. The transient at the output of the low-pass filter 9 reaches a maximum at times that are systematically delayed relative to the limits of the code words. The latency is determined by the PLL bandwidth per clock frequency. The differentiating unit 8 and the driver 7 carry out the calculation of the time of the maximum of the transient process at the output of the low-pass filter 9 and at this moment issue

through the open control unit 6, pulses to the installation input of the memory bandwidth generator contained in block 5. It is assumed that these pulses establish a combination in it that corresponds to the required systematic delay from the beginning of the code word, after which this generator produces a reference memory bandwidth, starting with the installation combination . In this way, the reference bandwidth is entered into synchronism with the received one.

In synchronization mode, the signal on the presence or absence of synchronization from the output of information extraction unit 4 disables the output of the imaging unit 7 from the setup input of unit 5. At the same time, the synchronous reference bandwidth is synchronized only by block 5. At the same time, the received memory bandwidth is demodulated using a synchronized reference bandwidth from the phase-shift keyed signal.

In the event of a synchronization breakdown, the allocation unit 4 of the | | formation provides a corresponding signal to the input of the control unit 6, which again connects the setup input of the unit 5. to the forced synchronization channel.

Claims (1)

Claims A device for receiving pseudo-random phase-shift keyed signals comprising a first multiplier connected in series, a phase locked loop and a synchronous detector, the second input of which is connected to the first input of the first multiplier, the second input of which is connected to the first input of the information extractor and the first output of the delay tracking unit, the first input of which is connected to the output of the synchronous detector and the second input of the information extraction unit, the output of which is connected to the first input of the control unit, the output of which is connected to the second input of the delay tracking unit, and the second input of the control unit is connected to the output of the signal conditioner, the input of which is connected to output of the differentiating unit, the input of which is connected to the output of the first low-pass filter, whose input is connected to the output of the phase detector, whose inputs are connected respectively to the outputs of the second multiplier and the clock generator, to the input of which the output of the first low-pass filter is connected, while the output of the delay element connected to the first input of the second multiplier, the second input of which is connected to the input of the delay element, characterized in that, in order to reduce the timing of synchronism, serially connected frequency multipliers are introduced, a third multiplier, a second low-pass filter, a controlled oscillator, a mixer and a band-pass filter, an output which is connected to the input of the delay element, the second output of the delay tracking unit and the first input of the first multiplier are connected respectively to the input of the frequency multiplier and the second input of the mixer, and the output of the second multiplier is connected to the second input of the third multiplier. Sources of information taken into account in the examination 1. USSR author's certificate No. 555556, cl. H 04 L 27/22, 1975 (prototype).