SU1385317A1 - Discrete frequency-modulated signal receiver - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to receive a signal with large phase fluctuations by reducing the signal search time. The receiver contains multipliers 14, 17, 40 and 44, delay blocks 25-27, switches 29 and 30, frequencies, r-words 31 and 32 of the number sequence, frequency grid former 33, frequency divider 38, adders (C) 39 and 43, controlled clock Mr. 49. Introduced Uz.-. band-pass filters 15, 18, 41 and 45, amplitude detectors 16, 19, 42 and 46, subtract-; there are blocks 20 and 47, threshold blocks 21 and 23 C 22, a driver of 24 trigger pulses, a delay block 28, a decoder 34, a multiplexer 35, a counter of 36 steps, a divider 37, a low-pass filter 48, diff. block 50, comparator 51 zero, elec I 52. In the transmitting device an abrupt multiples of 2 (t 1, 2, ...) increase in the base of the signal occurs, in the receiver - the corresponding following increase in the base of the reference signal, resulting in the degree of discrimination increases. xy-ki (increases the accuracy of the estimated delay of the received signal) of the delay tracking circuit. This is achieved by the coordinated operation of the transmitter and receiver units. 2 Il. with (L

Description

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The invention relates to radio engineering and can be used to transmit discrete information.

The purpose of the invention is to receive sigial pr large phase fluctuations by reducing; PIA time search sigiala.

FIG. 1 shows a structural electrical transmitter circuit; in fig. 2 - structural electrical diagram of acceptance.

The transmitter contains a generator of the I clock frequency, a divider 2 frequencies, a divider 3 ,; multiplexer 4, a counter of 5 stages, a generator of 6 single pulses, the first and second generators 7 and 8 of the sequence of numbers, the first and second switches 9 and 10, reflect its state, and since the outputs of the bits of the counter 5 are connected to the control inputs of the multiplexer 4, in accordance with the state of the counter 5, the corresponding information inputs of the multiplexer 4 are connected to the generators 7 and 8 of the sequence of numbers. Such a switch leads in turn to an increase in the clock frequency of the generators 7 and 8 at each stage, and consequently, to an increase in the frequency of the sequence of numbers N and NJ. This leads to a projective increase in the steepness of the correlation characteristic of the emitted signals. In iriemnik there is an aiomourer 11 of the frequency grid, a multiplexer is equipped with a 36-stage counter, dividing 12, a power amplifier 13 and 37, a multiplexer 35 and generators 31

The receiver contains the first multiplier 14, the first narrow-band filter 15, the first amplitude detector 16, the second multiplier 17, the second narrow-band filter 18, the second amplitude detector 19, 20 the first subtractive unit 20, the second threshold unit 21, the third adder 22, the first threshold unit 23, shaper 24 Pulses start, the first, second, third, fourth blocks 25-28 delay, the first, second switches 29 and 30 frequencies, the first, second generators 31 and 32 follower

25

numbers, shaper 33 of the frequency grid, decoder 34, multiplexer 35, counter 36 stages, divider 37, divider 38 frequency.

and 32 sequences of numbers, which leads to an increase in the steepness of the discriminatory characteristic, and, accordingly, to an increase in the accuracy of Leaving for the delay of the received signal of the delay tracking circuit (blocks 39-49). This leads to the fact that the received and reference signals are computed to the accuracy of the tracking error of the delay tracking circuit. In the initial state (first stage), the HacTpoeif receiver to the first frequency of the first sequence of numbers N, is similar to the initial setup of the transmitting device, i.e., the transmission starts from the same frequency of the first sequence. There are 32 number sequences for launching the fori, which leads to an increase in the slope of the discriminating characteristic, and, accordingly, to an increase in the accuracy of the Delay for the delay of the received signal of the delay tracking circuit (blocks 39-49). This leads to the fact that the received and reference signals are computed to the accuracy of the tracking error of the delay tracking circuit. In the initial state (first stage), the HacTpoeif receiver to the first frequency of the first sequence of numbers N, is similar to the initial setup of the transmitting device, i.e., the transmission starts from the same frequency of the first sequence. For the start, the first adder 39, the third displacer 30. World 24 uses siglasovanny

40, the third narrow-band filter 41, the third amplitude detector 42, the second adder 43, the fourth multiplies spruce 44, the fourth narrow-band filter 45, the fourth amplitude detector 46, the second subtract the filter (blocks 14-19, 22) with the threshold block 23 at the output together with the circuit run (blocks 50-52), which is triggered from the first sequence of numbers N, because it is connected to the first information45

block 47, a low-pass filter 48, up to the 35th channel (blocks 14–16), which extracts a clock generator 49 from a differential, a differentiating block 50, a comparator 51 zero, an And 52 element.

The proposed device works as follows. 40

In the transmitting device, a jump-like multiple of 2 occurs, where m is 1,2, 3 ...., the base of the signal increases, and in the receiver, a corresponding increase in the base of the reference signal, resulting in an increase in the slope of the discriminatory characteristic (accuracy increases estimation of the delay of the received signal of the delay tracking circuit. This is achieved by the coordinated operation of the transmitter and receiver units.

In the transmitter, at the initial moment of time, the signal from the generator of 6 single pulses sets the counter of 5 stages, divisor 3 and generators 7 and 8 of the sequence of numbers to the initial state.

After that, the last bit of output, 55 and divisor 3, receives impulses that define the boundaries of the stages. These pulses, arriving at the counting input of the counter 5 stages.

signal-to-noise mixture, a signal modulated by the sequence N, from which the first stage of the transmission begins. Thus, the receiver starts with the start of a matched filter and the driver 24 start circuit, as a result of which the clock frequency of the generators 31 and 32 starts to increase from stage to stage. To eliminate discontinuities of the signal phase, at the moments of frequency switching, a constant divider 38 is used. division, which is selected to provide the desired frequency ratio of the signal. The transmission of the sequence N is repeated (with a reset at the beginning of each stage) until the receiver tracking error reaches a predetermined value. Due to the doubling of the supply frequency of generators 31 and 32, the duration of the stage is twice as large as the elements of the sequence N1.

Claims (1)

Invention Formula The receiver of discrete frequency-modulated signals containing control of its state changes, and since the bits of counter 5 are connected to the control inputs of multiplexer 4, in accordance with the state of counter 5, the corresponding information inputs of multiplexer 4 are connected to generators 7 and 8 sequences of numbers. Such a switch leads in turn to an increase in the clock frequency of the generators 7 and 8 at each stage, and consequently, to an increase in the frequency of the sequence of numbers N and NJ. This leads to a projective increase in the steepness of the correlation characteristic of the emitted signals. In iriemnik there is a similar operation of a counter of 36 stages, a division of 37, a multiplexer 35 and generators 31 the operation of the counter is 36 steps, a division of 37, multiplexer 35 and generators 31 and 32 sequences of numbers, which leads to an increase in the steepness of the discriminatory characteristic, and, accordingly, to an increase in the accuracy of Leaving for the delay of the received signal of the delay tracking circuit (blocks 39-49). This leads to the fact that the received and reference signals are computed to the accuracy of the tracking error of the delay tracking circuit. In the initial state (first stage), the HacTpoeif receiver to the first frequency of the first sequence of numbers N, is similar to the initial setup of the transmitting device, i.e., the transmission starts from the same frequency of the first sequence. Shaper 24 is used to start shaper. worldizer 24 uses siglasovanny the filter (blocks 14-19, 22) with the threshold block 23 at the output together with the startup scheme (blocks 50-52), which is triggered from the first sequence of numbers N, because it is connected to the first information channel (blocks 14-16), is allocated from five 5 th channel (blocks 14-16) allocating from 0 d signal-to-noise mixture, a signal modulated by the sequence N, from which the first stage of the transmission begins. Thus, the receiver starts with the start of a matched filter and the driver 24 start circuit, as a result of which the clock frequency of the generators 31 and 32 starts to increase from stage to stage. To eliminate discontinuities of the signal phase, at the moments of frequency switching, a constant divider 38 is used. division, which is selected to provide the desired frequency ratio of the signal. The transmission of the sequence N is repeated (with a reset at the beginning of each stage) until the receiver tracking error reaches a predetermined value. Due to the doubling of the supply frequency of generators 31 and 32, the duration of the stage is twice as large as the elements of the sequence N1. Invention Formula A discrete frequency-modulated signal receiver containing a controlled clock generator, the output of which is connected to the inputs of a frequency divider and a frequency grid former, the outputs of which are connected to the first inputs of the first and second frequency switches, the second inputs of which are connected to the outputs of the first and second number sequence generators, first, second, third delay blocks, first, second, third, fourth multipliers, the first inputs of which are combined the input element And the first input of the trigger pulse generator, the second and third inputs of which are connected respectively to the output of the element And and the output of the controlled clock generator, the output of the third delay unit through the first delayed unit, the second adder, the fourth multiplier, the fourth narrow-band filter and the fourth the amplitude detector is connected to the first and are the receiver input discrete input of the second subtractive unit, the output of the frequency-modulated signals, the first, fourth delay unit through the second second adders, characterized in that, in order to receive a signal with large phase fluctuations, by reducing the time the delay unit is connected to the second input of the second adder, the output of the first frequency switch is connected to the input of the third search, the first, second, third and 15 delay units and the first input of the first fourth narrowband filters are entered, the first, adder, output of the second switch is the second, third and the fourth amplitude child is connected to the input of the fourth block of the detectors, the first and second subtractive blocks and the second input of the first adder, ki, the first and second threshold blocks, the output of which through the sequencer trigger pulse, the decoder, the third multiplier single, t, retiy uz multiplexer, stage counter, divider, band-pass filter and the third amplitude low-pass filter, the third adder, the detector is connected to the second input of the second fourth delay block, differential-subtracting block whose output through a block comparator zero, element I, a second low-pass filter connected to the input ry inputs of the first and second multiply-controlled clock oscillator, output lei connected to the outputs of the third and fourth pulse former the start is connected to the delayed delay units, the output of the first with the first inputs of the stage counter, the divider, both generators of sequences of numbers, the second inputs of which are connected to the output of the multi plexer, the output of the frequency divider is connected to the second input of the divider, one output of which is connected the outputs - with the permultiplier through the first narrowband filter and the first amplitude detector connected in series with the first inputs of the p & subtractive blc and the third adder, the output of the second The second multiplier filter and the second amplitude detector are connected to the second inputs of the first subtractive unit and the third adder; the output of the first amplitude detector is connected via a serially connected differentiating unit and the comparator zero is connected to the first input of the element I; the output of the third adder is connected to the first threshold unit the second thirty 35 the output inputs of the multiplexer, the second inputs of which and the inputs of the decoder are connected to the outputs of the stage counter, the output of the first subtraction unit is connected to the input of the second threshold unit whose output is the first output of the receiver of discrete frequency modulated signals, the second output of which is the output of the decoder. the input element And the first input of the trigger pulse generator, the second and third inputs of which are connected respectively to the output of the element And and the output of the controlled clock generator, the output of the third delay unit through the first delayed unit, the second adder, the fourth multiplier, the fourth narrow-band filter and the fourth the amplitude detector is connected to the first five the output inputs of the multiplexer, the second inputs of which and the inputs of the decoder are connected to the outputs of the stage counter, the output of the first subtraction unit is connected to the input of the second threshold unit whose output is the first output of the receiver of discrete frequency modulated signals, the second output of which is the output of the decoder.