SU1241519A1 - Demodulator of phase-shift keyed signal - Google Patents

Abstract

The invention relates to radio engineering. Reliability is increased by eliminating information ambiguity when demodulating a phase-shifted signal with a manipulation index P / n, where n is any number 1, unequal 2. The device contains two frequency multipliers I and 5, narrowband filter 2, four phase detectors 3, 10, 15 and 17, two phase shifters 4 and 18, controlled oscillator 6, two low-pass filters 8 and 16. The goal is achieved by introducing a delay element of 2, 2 keys 7 and 14, an element of OR 13, 2 threshold blocks 12 and 20 , 2 LPF P and 19 and the adder 9. 1 Il. ate with

Description

The invention relates to radio engineering and can be used to create radio complexes using phase-shift keyed signals.

The purpose of the invention is to increase the reliability by eliminating the ambiguity of information when demodulating the phase-shifted signal c; index manipulation P / n, where n is any number greater than one, unequal to two.

The drawing shows a structural electrical circuit of the proposed demodulator.

The demodulator contains the first frequency multiplier 1, narrowband filter 2, the first phase detector 3, the first phase shifter 4, the second frequency multiplier 5, the controlled oscillator 6, the second key 7, the first low frequency filter 8, the adder 9, the second phase detector 10, the fourth low frequency filter 11, first threshold unit 12, element OR 13, first key 14, third phase detector 15, second low frequency filter 16, fourth phase detector 17, second phase shifter 18, third low frequency filter 19, second threshold unit 20, element delay 21

The demodulator works as follows.

In the absence of a signal, key 14 is open and key 7 is closed. The phase shift keyed signal in frequency multiplier 1 is multiplied n times, as a result of which the phase shift is removed. The p-harmonic of the carrier frequency of the signal, passing through the narrowband filter 2, enters the input of the phase detector 3, where it is compared to the frequency of the controlled oscillator 6, multiplied n times in the multiplier 5 frequency and passed through the phase shifter 4 by P / 2. The beat voltage through the public key 7, the low-frequency filter 8 and the adder 9 is fed to the input of the controlled oscillator 6. In the case of frequency. beat does not exceed the capture band of the phase-locked loop system after some time, the phase-locked loop (PAD) system is in sync. The frequency of the controlled oscillator 6 is equal to the carrier frequency of the input phase-manipulated signal, and the spacing

1241519. i

oscillation phases at the inputs of the detector 3 is equal to

phase

.l D

I i 2

+ .D and) y

where is the initial frequency difference

c

 at the inputs of the third phase detector prior to entering synchronization; retention band of the FAL system.

With an appropriate choice of the parameters of the PLL system, the Pz value can be obtained close to P / 2. At the inputs of the phase detector 10, the signals are shifted relative to each other by

H A + - to-in synchronism mode

but

2

five

At the output of the FAP system, a constant voltage close to the maximum value is found. This constant voltage, having passed through the low frequency filter I1 and exceeding the threshold of the threshold unit 12, through the OR 13 element enters the control input of the key 5 14 and opens it. The input signal through the public key 14 is fed to the second input of the phase detector 15 and through the phase shifter 18 to П / 2 to the second input of the phase detector 17, to 0 other inputs of which the voltage of the controlled oscillator 6 is fed, whose frequency is equal to the carrier frequency of the input signal. After some time, the second PLL system (phase detector 15, low-frequency filter 16, adder 9, controlled oscillator 6) enters synchronization. The bandwidth of the second system must not exceed the value of the lowest modulation frequency. When the second FAL system is in synchronism, the output of the phase detector 17 is a constant voltage, which, having passed through the low-frequency filter 19, will exceed the threshold of the threshold unit 20, through the OR element 13 will go to the control input of the key 14. After opening the key 14 after the time required for the second PLL system to enter into synchronization and equal to the time delay value of the delay element 21, the voltage from the phase detector 10 opens the switch 7, and the first PLL system is turned off. As a result, only the second PLL system remains operational. The required state of the keys 14 and 7 (the key 14 is closed, and the key 7 is open) is pooled using the output voltage 0

five

0

five

phase detector detectors 17. In this case, the phase of the output voltage of the controlled oscillator 6 is different from the phase of the carrier frequency of the signal and the value is close to G) / 2. After the second PLL system is in sync with the output of the phase detector 15, information is acquired.

Claims (1)

Invention Formula A phase-shift demodulator containing the first and second low-pass filters, two frequency multipliers, a narrow-band filter, four phase detectors, two phase shifters, and a controlled oscillator, characterized in that, in order to increase reliability by eliminating information ambiguity during phase demodulation of the manipulated signal with the manipulation index, where n is any layer greater than one, unequal to two, a delay element, two keys, an OR element, two threshold blocks, the third and fourth filters are often low you and an adder, the output of the first frequency multiplier is connected via a narrow-band filter to the first inputs of the first and second phase detectors, the output of which is connected in series through the fourth low-frequency filter and the first threshold unit to the single input of the OR element, output Editor T. Parfenova Compiled by N. Lazarev Tehred O. Gortvay Order 3616/58 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 13035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 . five Yu which is connected to the first input of the first key and through series-connected delay element, the second key and the first low frequency filter to the first input of the adder, the output of which is connected to the second input of the first through a serially connected controlled oscillator, torus, second frequency multiplier and first phase shifter phase detector, the output of the first key is connected to the first input of the third phase detector and through the second phase shifter - to the first input of the fourth) 5 phase detector, the output of the controlled oscillator with connected with the combined third inputs of the third and fourth phase detectors, the output of the third phase detector is the output of the device, and through the second low-pass filter is connected to the second input of the adder, the output of the fourth phase detector is connected through the third low-pass filter connected in series and the second threshold unit is connected to another input of the OR element, and the input of the first frequency multiplier and the second input of the first key are combined and are the device input; the output of the first phase detector is connected to the other input of the second switch, and the output of the second frequency multiplier coupled to a second input of the second phase detector. 0 five 0 five Proofreader M. Demchik