SU773946A1 - Synchronizing device - Google Patents

Synchronizing device Download PDF

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Publication number
SU773946A1
SU773946A1 SU792729035A SU2729035A SU773946A1 SU 773946 A1 SU773946 A1 SU 773946A1 SU 792729035 A SU792729035 A SU 792729035A SU 2729035 A SU2729035 A SU 2729035A SU 773946 A1 SU773946 A1 SU 773946A1
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SU
USSR - Soviet Union
Prior art keywords
synchronizing device
channels
input
frequency
input key
Prior art date
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SU792729035A
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Russian (ru)
Inventor
Юлюс Антано Гвергждис
Альгимантас Антано Каяцкас
Original Assignee
Каунасский Политехнический Институт Им.Антанаса Снечкуса
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Priority to SU792729035A priority Critical patent/SU773946A1/en
Application granted granted Critical
Publication of SU773946A1 publication Critical patent/SU773946A1/en

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Description

(54) УСТРОЙСТВО СИНХРОНИЗАЦИИ(54) SYNCHRONIZATION DEVICE

1one

Изобретение относитс  к радиотехнике и может использоватьс  в системах передачи дискретной информации с временнйм уплотнением.The invention relates to radio engineering and can be used in systems for transmitting discrete information with a time seal.

Известно устройство синхронизации, содержащее п каналов, каждый из которых состоит из последовательно соединенных входного ключа, первого делител  частоты, фазового дискриминатора и усилител , а также управл ющий элемент, объединенный по входу с входным ключом, при этом выходы управл ющего элемента подключены к другим входам входного ключа и первого делител  частоты, причем выходы всех каналов подключены к входам сумматора , выход которого через последовательно соединенные фильтр нижних частот, управл емый генератор и второй делитель частоты подключен к другим входам фазовых дискриминаторов и управл ющих элементов всех каналов ij .A synchronization device is known that contains n channels, each of which consists of a serially connected input key, a first frequency divider, a phase discriminator and an amplifier, as well as a control element integrated in the input with the input key, while the outputs of the control element are connected to other inputs the input key and the first frequency divider, the outputs of all channels are connected to the inputs of the adder, the output of which is through a series-connected low-pass filter, a controlled oscillator and a second one frequency fir connected to the other input of the phase discriminator and the actuating elements of all channels ij.

Однако известное устройство обладает низкой надежностью работы в услови х измен ющейс  (нестабильности) частоты поступающего синхросигнала и низкой точностью синхронизации.However, the known device has low reliability in the conditions of varying (instability) frequency of the incoming clock signal and low synchronization accuracy.

Цель изобретени  - повышение точности синхронизации.The purpose of the invention is to improve the synchronization accuracy.

Claims (1)

1. Патент ФРГ № 1591593, кл. Н 04 J 3/06, 1977 (прототип).1. Patent of Germany No. 1591593, cl. H 04 J 3/06, 1977 (prototype).
SU792729035A 1979-02-23 1979-02-23 Synchronizing device SU773946A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU792729035A SU773946A1 (en) 1979-02-23 1979-02-23 Synchronizing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU792729035A SU773946A1 (en) 1979-02-23 1979-02-23 Synchronizing device

Publications (1)

Publication Number Publication Date
SU773946A1 true SU773946A1 (en) 1980-10-23

Family

ID=20811969

Family Applications (1)

Application Number Title Priority Date Filing Date
SU792729035A SU773946A1 (en) 1979-02-23 1979-02-23 Synchronizing device

Country Status (1)

Country Link
SU (1) SU773946A1 (en)

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