SU1297249A1 - Device for reception of frequency-shift-keyed signals - Google Patents

Description

The invention relates to radio and can be used in the equipment for receiving discrete information transmitted by frequency-manipulated signals.

The purpose of the invention is to expand the functionality by receiving a multi-position signal.

Figure 1 shows a structural electrical circuit of the proposed device; FIG. 2 is a block diagram of a clock synchronization block.

The device for receiving frequency-manipulated signals contains two channels consisting of multipliers 1.2, low-pass filters 3.4, decision blocks 5, 6, the first multiplier 7, the second multiplier 8, additional low-pass filter 9, controlled generator 10, second phase shifter II, clock synchronization unit 12, third phase shifter 13, first phase shifter 14, first and second modulators 15.16 modulo two, additional channels consisting of multipliers 17.18, filters, low frequencies 19, 20 , blocks 21, 22 make decisions. neither, frequency multiplier 23 by two, frequency divider 24 by two, the third multiplier 25, bandpass filters 26,27, switch 28, block 12 consists of band-pass filter 29, frequency discriminator 30, frequency multiplier 31 by two, synchronously tracking filter 32 and frequency divider 33 into two.

The device works as follows.

The received four-way frequency-manipulated signal: a signal containing the symbol frequencies f, fj, f ,, f ,, is fed to the first inputs of multipliers 1, 2 ,. moreover, f, f fr; f.

o 4 T

f + 7 f; 04 T

-

0+ l T ya

f is the carrier frequency, and f is the clock frequency. The multipliers 1 and 2, low-pass filters 3 and 4, the first and second multipliers 7 and 8, the additional low-pass filter 9, the controlled oscillator 10, the second and third phasers 11 and 13 by 90 and the clock synchronization block 12 form a modified Costas ring, which highlights the carrier signal

,

p a- fO

. 15

20

25

thirty

35

40

45

50

fg, synchronous with the received signal. In this case, it is possible to receive information on the polarity of the output voltage in the code of low-pass filters of the 3rd and 4th quadrature channels of the ring. The decision on the acceptance of the symbols is taken alternately at the clock interval by means of decision blocks 5, 6, which are clocked with a half-clock frequency by the output signal of the clock synchronization block 12. In this case, block 5 is clocked by an inverted signal from the output of the phase shifter 14 to 180. The information from the first and second channels is combined with modulators 15.16, modulo two, and with the aid of the adder 1 5, the rearrangement; relative decoding is eliminated, which eliminates the phase uncertainty by 180 that occurs in the costas ring generator 10, and with the help of the adder 16, taking into account the phase shift during the previous clock interval. One of the logic levels at the output of adder 16 corresponds to the fact that the received frequency belongs to the group f, f, and the opposite level corresponds to that it belongs to the group f J, 1.; To distinguish the frequencies of group f,, f, the third channel serves, and to distinguish frequencies f,

f is the fourth channel. Using a band-pass filter 26, the reference signal is selected with a frequency f for the third channel, and With the power of the bandpass filter 27, a signal with a frequency f, for the fourth channel, is extracted. The inputs of filters 26 and 27 receive the product of signals with a frequency fg from the output of the controlled oscillator 10 and with a frequency of m / 4 from the output of the frequency divider 24 by two. The decision on the received symbols is made using blocks 21, 22 simultaneously at each clock interval. A clock signal with a clock frequency enters the output t of frequency multiplier 23 by two. In this case, the frequencies f J and f. matches level

55

, and frequencies f, and f - level O. Depending on which group of frequencies the received signal belongs to, the output is connected either to the output of the device or to the output of one or another channel via switch 28, which is controlled by a signal from the output of the adder 16 modulo two. Thus, the output of the adder I6 modulo two and the output of the switch 28, which are the outputs of the device, removes information in the parallel code corresponding to the frequency of the received frequency-manipulated signal.

The clock synchronization unit operates as follows.

The input signal passes through the band-pass filter 27 and enters the frequency discriminator 30. From the output of the frequency discriminator, the signal goes to frequency multiplier 29, while the spectrum of the signal to the output of frequency multiplier 29 contains a discrete component with a clock that is tracked synchronously. filter 32. To obtain a half-frequency frequency, the signal from the output of the synchronously tracking filter 32 is fed to a frequency divider 33 by two, the output of which is the output of the block.

Claims (2)

Invention Formula one . A device for receiving frequencies of but-manipulated signals containing two channels, each of which consists of a serially connected multiplier, a low-pass filter and a decision block, the outputs of decision blocks are connected to the corresponding inputs of the first modulo-two adder, whose output is connected to the first input of the second modulo two adder, the second input of which is connected to the output of the clock synchronization unit, which is connected to the second input of the decision unit of the first channel and through the first phase The rotator with the second input of the second channel decision block, the first multiplier connected in series, the second multiplier, additional low pass filter, controlled generator and second phase shifter whose output is connected to the first input of the second channel multiplier, connected to the first generator the input of the multiplier of the first channel, the second inputs of the multipliers of the first and second channel and the input of the clock synchronization unit are combined and are the input of the device, the output of the clock synchronization unit through the third phase shifter is connected to the second input of the second multiplier, the low-pass filter outputs are connected to the corresponding inputs of the first multiplier, the output of the second modulo-two is the first output of the device, characterized in that, in order to extend the functionality by receiving a multi-position signal, introduced two additional channels consisting of a series-connected multiplier, a low-pass filter and a decision block, as well as two band-pass filters, t The multiplier, the frequency divider by two, the frequency multiplier by two, and the switch; the outputs of the decision blocks of the first and second additional channels are connected respectively to the first and second inputs of the switch; the output of which is the second output of the device; the first inputs of the additional channel multipliers are connected the input of the device, the output of the third multiplier through the corresponding bandpass filters is connected to the second inputs of the multipliers of the additional channels, the output of the clock synchronization unit and through a frequency divider by two connected to the first input of the third multiplier, the second input of which is connected to the output of the controlled generator, the output of the clock synchronization unit through the frequency multiplier to two connected to other inputs of the decision blocks of additional channels. 2. The device according to claim 1, wherein the clock synchronization unit consists of a series-connected band-pass filter, a frequency discriminator, a frequency multiplier by two, a synchronously tracking filter, and a frequency divider by two, with the input of the band-pass filter and the output of the frequency divider by two is respectively the input and output of the clock synchronization unit FIG. 2