SU486486A1 - Synchronous receiver of the phase-shift keyed signal - Google Patents

Description

one

The invention relates to radio engineering and can be used to transmit discrete 1P1 information over radio paths, and including over paths with variable parameters.

A synchronous receiver of a phasomaniac signal is known, containing a parallel 110 connected in-phase and quadrature channels, to the output of which are connected successively connected a dry mattor and a decision circuit, each of the said channels containing a series-connected nerve multiplier with but not connected to its second input by a generator of reference voltage a matched filter, a second non-multiplier with an integrator connected to its second input.

However, in a known device, an integrator with a large time constant accumulates a voltage that, in the absence of a map, is proportional to the cosine (or sine in the quadrature channel) of the phase difference between the voltage of the received signal and the reference oscillator, with error, which significantly reduces the immunity of the received information.

The purpose of the invention is to improve noise immunity.

For this, in each channel between the said matched filter and the integrator, connected in series are the first key, a packer, the second key and the sign multiplier, and the control inputs of the first keys and the decision circuit are connected to the nerve output of the second keys and the second key the input of the external synchronizer, and the output of reschayuyn-1, the circuit is connected to the control inputs of the sign multiplier.

Jia drawing shows a structured electrical circuit of a synchronous receiver.

A synchronous receiver of a phase-shift keyed signal contains an in-phase 1 and quadrature 2 channels, each of which contains successively connected first multiplier 3, matched filter 4, first and second current switches 5 and b, a diagonal reparator 7, N tegrator 8, a second repostor 9, with this .m output matched filter 4 is also connected to another input of the non-multiplier 9 n output of the first current switch 5 is shunted by a storage capacitor 10. The outputs of the second multipliers 9 channels 1 and 2 are combined using adder II, to the output which the decision circuit 12 is connected, and its output is the output of the synchronous receiver. At the same time, the output of the solving circuit 12 is connected to the combined control inputs of the sign multipliers of 9 channels 1 and 2, and the control input

it is connected to the combined control inputs of the first current switches 5, the control inputs of the second current switches 6 are also integrated. One of the inputs of the first multipliers 3 of channels 1 and 2, which are connected together, are the receiver's ingress input.

The reference generator 13 is directly connected to the second input of the first non-multiplier 3 of the in-phase channel 1 and through the phase shifter 14 is connected to the second input of the nerve intermotor 3 of the quadrature channel 2.

The operation of the synchronous receiver is as follows.

The signal arriving at the signal input of the receiver, which is a radio) 1Mpuls, manipulated in phase, is fed to the inputs of non-multipliers 3 in-phase 1 n quadrature 2 channels, where it multiplies with the voltage of the reference generator 13, whose frequency is equal to the frequency of the received signal, and phase random. Voltage module of the multiplier output 3 channel 1 ipopordioyala scalar product of the incoming and support signals, and the output of the multiplier 3 dripped 2 - incoming and reference, shifted 90 ° phase by the phase shifter 14. Output signals of multipliers 3 in drops 1 and 2 post on matched filters 4 that implement their optimal filtering. The filtered signals butto one of the inputs of the second multiplier 9, the outputs of which are combined by the adder 11.

To the other inputs of multipliers 9, the signal in each of the channels 1 and 2 from the matched filter 4 passes through the first current switch 5, the second current switch 6, the sign multiplier 7, and the integrator 8 in series. The current switch 5 opens with a pulse arriving at its control input from the external synchronous device at the moment corresponding to the maximum of the signal at the output of the matched filter 4. In this case, accumulative capacitance 10 is charged to a value equal to the maximum of the signal. The charge on the capacitor 10 is kept until it is discharged through the current switch 6, which is opened when the second synchronizer arrives at its control input. The second clock pulse is shifted in time by the interval necessary for the decision of the sign of the received parcel. The discharge of the capacitance 10 is accompanied by the appearance at the output of the current key 6 of an impulse whose value is equal to the voltage on the capacitance 10 until the moment of discharge. The impulse from the current key 6 will be transferred to the symbolic multiplier 7, ocyniecTBl yuidy, the phase locking system. The output signal of the cereal transceiver 7, has the form of a pulse, the amplitude of which is the niordioalpal module of the caloric production of voltages and iormal signals, accumulates on the integrator 8, produces n; prynogo izizveneni come sigiala and sipfaznoy (or square) komioneitoy reference siala. Changes in the sign of this example;.; The wives are determined by the manipulation of the transmission.

The output signals of the multipliers 9, kayals 1 and 2, folded by summator-i 11, are sent to decisive exema 12, which is a bipolar threshold device, which is responsible for deciding the sign of the received message. The decision is made at the first moment of the maximum of the irradiated sigial, for which the solving scheme 12 is also sihihroizirovana the first imiulis external S1P chroniizator. The output voltage of the circuit 12 is supplied to the control inputs of the ziak and multipliers 7 for the TL of the manipulation, and also is - output pa; 1p; The solution of the entire siphropi irieemika phase-pipuli) ovappo1o signal.

P r with, t mme and 3 about b I) e s vulture

Synchrophase receiver of the phase-shift key signal, soda genre, and in parallel to the input and connection of the phase and quadrature channels, to the output of which are connected in series an adder and a solver; each of the channels mentioned contains successively connected: a single nerve multiplier with a generator connected to its second input (a pure voltage, a matching filter, a single interrupt gun with an integrator connected to its second input, in order to increase the noise immunity, in each channel between the said matching filter and the integraiop are connected in series the first key, tip, second key and symbolic multiplier, and to the control, their first inputs yuchey and decisive circuit podklyuchep nerve siphroppzatora external output, to the control inputs of the second switch is connected a second input of the external synchronizer, and the output circuit nodklyuchen decisive for the control vhod.am ziakovogo perempozhptel.