SU443455A1 - Device for coherent reception of phase-shift keyed signals - Google Patents

Description

one

The invention relates to telecommunications can be used in receivers with relatively phase-mapped signals.

The known devices for coherent iriem phasomai and auline signals contain two signal processing subchannels - in-phase and quadrature, as well as a local oscillator with an oscillation frequency equal to the frequency of the received signal, which is connected to the si-phase subchannel and means, and to the quadrature subchannel through a 90 ° phase shifter. Each subchannel of such a device contains a series of coefficients, integrators, auxiliary and symbolic multipliers, as well as a series of rectifiers, integrators, and compensators connected between the integrator input and the second input of the equivalent multiplier. The device also contains a cross factor multiplier, coupled with the outputs of the pre-lending intermultipliers, to which the integrator of the restraint channel is connected and consistently decisive. The outputs of the channel channels are combined by an adder, at the output of which a decoder is installed.

The disadvantage of such a coherent process is the low reliability of the emission of the source voltage, which leads to the appearance of additional errors at the channel output, reducing the reliability of the received information.

The aim of the invention is to increase the reliability of the allocation of the oral frequency.

In the invention, this goal is achieved by connecting between an omnipotent decisive circuit and a second input of a sign multiplier of a quadrature iodchannel of a countable trigger, and also including a second sign multiplier of a second input of which is connected to a common in-subchannel subchannel and which has a heart of a connected charger.

The drawing shows a structural diagram of the proposed device for the coherent reception of phase-locked controls.

The device contains non-multipliers 1 n 2 in-phase n quadrature subchannels, one inputs of which are interconnected n are the input of the device, and the other nx inputs are connected to the local generator 3 both directly and through the phase shifter 4. In each of the subchannels in series with the multiplier m 1 and 2 includes integrators 5, 6, additional multipliers 7, 8, and sign multipliers 9 and 10. In each subchannel between the output of the integrator 5 and 6 and the second input of the additional multiplier 7, 8 are connected in series e vynr DC converter 11, 12, integrators 113, 14 and 15 compensators and 1b. The outputs of the additional multipliers 7 and b are connected to the inputs of the cross multiplier 17, in series with which the integrator of the cross channel 18 and the auxiliary decision circuit 19 are connected. Between the auxiliary decision circuit 19 and the second input of the sign multiplier 10, the counting trigger 20 is connected, the output and input of which are connected inputs additional sign multiplier 21, the output of which is connected to the second input of the sign multiplier 9. The outputs of the sign multipliers 7 and 8 are connected by an adder 22, to which connected decoder 23.

The incoming signal enters the inputs of the switches 1 and 2 and multiplies with the signal of the local generator 3, the frequency of which is equal to the frequency of the signal, and the phase is random. In this case, the phase of the local generator signal applied to multiplier 2 is shifted by 90 by phase shifter 4 relative to the signal applied to multiplier 1. Output voltage from multipliers 1 and 2 is filtered by integrators 5 and 6, which are filters matched with the envelope of a single received signal. The output voltage of the integrators goes to one of the inputs of additional multipliers 7 and 8, and then to one of the inputs of the sign multipliers 9 and 10. Simultaneously, from the output of integrators 5 and 6, the voltage is proportional to the cosine of the phase difference between the received signal and a local oscillator signal 3, and in a quadrature - a sine, is fed to rectifiers 11 and 12, which carry out the phase shift of the signal. The output voltage of the rectifiers 11 and 12 is additionally filtered by the integrators 13 and 14, which have a large time constant. To compensate for the constant component of the noise voltage due to the presence of rectification of the signal and noise mixture, compensators 15 and 16 are used. From the output of the compensators 15 and 16, the voltage goes to the second inputs of the additional multipliers 7 and 8. 7 is normal to the product of the power received by the device by the square of the cosine of the phase shift between the received signal and the local oscillator signal, and changes in the sign of this magnitude are determined by the manipulation on transmission. In the quadrature subchannel at the output of the additional multiplier 8, the signal magnitude is proportional to the product of the received signal power by the square of the sine of the phase difference.

At the same times, the signs of the output voltages of the additional multipliers 7 and 8 may differ, which is determined by the absolute value of the said phase difference. To match the subchannels by the sign of their output voltages, these voltages are fed to the cross-multiplier 17, and then to the integrator 18. The output voltage of the integrator 18 has a positive polarity with the same voltage signs, in the subchannels, and a negative one with different ones. This circumstance determines the output voltage of the auxiliary decision circuit 19 installed at the output of the integrator 18. This voltage is fed to the counting trigger 20 and

additional sign multiplier 21. Counting trigger 20 is transferred from one state to another at times corresponding to a change in polarity of voltages in the in-phase or quadrature subchannels caused by the phase difference between the received signal and the local oscillator. The output voltage of the trigger controls the operation of the sign multiplier 10. The additional sign multiplier 21 also

serves to form the voltage controlling the operation of the sign multiplier 9.

The resulting signals of both subchannels are summed by adder 22, the output

the voltage of which in absolute value is proportional to the power of the received signal, and the sign is determined by the manipulation of the transmission. Allocation of information embedded in changes of this sign is performed by the decoder 23, the output of which is the output of the entire device.

Claims (1)

Invention Formula A device for coherent reception of phase-shift keyed signals, containing in-phase and quadrature subchannels sequentially connected permultipliers, integrators, additional and sign multipliers, as well as series-connected rectifiers, integrators and compensators connected between the output of the integrator and the second input of the additional multiplier, a local generator connected to to the multiplier of the in-phase subchannel and, through the phase shifter, to the multiplier of the quadrature drip, as well as the successor but connected cross-multiplier, connected to the outputs of additional multipliers, cross-channel integrator, auxiliary decision circuit, adder connected to the outputs of the sign multipliers, and the decoder of the relative phase manipulation, so that, in order to increase the reliability of the reference frequency allocation, between the auxiliary decisive circuit and the second input of the quad multiplier subchannel the counting trigger is switched on, and between the second input of the multiplicator and the synchro subchannel, the counting trigger is switched, subchannel included b additional character multiplier, the second input of which is connected to the output of the counting trigger. 7V-V4n-4 P Bash