SU1070683A1 - Frequency-or-phase-telegraphy signal demodulator - Google Patents

Abstract

A DEMODULATOR OF SIGNALS OF FREQUENCY AND PHASE TELEGRAPHY, containing successively connected limiter-shaper, shift register and the first signal processing unit, the second input of which is connected to the output of the limiter generator, while the second output of the shift register, he is connected to the first input of the second signal processing unit, and A manipulation filter, characterized in that, in order to improve the noise immunity, two inverters and two I elements are introduced, the outputs of the first and second signal processing units: s connected to the input dg1m of the first element And directly and to the inputs of the second element And through the inverters, the outputs of the elements And are connected to the corresponding inputs of the manipulation filter, which is made digital, the second input of the shift register is connected to the clock inputs of the first and second elements And, and the first output of the shift register (It is assigned to the input of the second signal processing unit. Eo ftfjvf DO

Description

The invention relates to communications and can be used in receivers of digital information transmission systems with frequency or phase modulation. The known demodulator of signals of frequency telegraphy contains a signal limiter, two nonlinear digital filters, a reference oscillator, two nodes — weight functions, and frequency divider C11. The closest to the present invention is a demodulator of frequency and phase telegraphy signals, containing a series-connected limiter-shaper, shift register, and a new signal processing unit, the second input of which is connected to the output of the limiter-shaper while the second output of the shift register is connected to the first the input of the second signal processing unit and the G21 manipulation filter. A disadvantage of the known demodulators is their low noise immunity. The purpose of the invention is to increase the noise immunity of the demodulator. The goal is achieved by the fact that a demodulator of frequency and phase telegraphy signals containing series-connected limiter-shaper, shift register and the first signal processing unit, the second input of which is connected to the output of the limiter-shaper, while the second output of the shift register is connected to the first input of the second signal processing unit, and a manipulation filter, two inverters and two I elements are introduced, with the outputs of the first and second signal processing units being connected to the inputs of the first element directly and to the inputs of the second element I through inverters, the outputs of the elements AND are connected to the corresponding inputs of the manipulation filter, which is digital, the second input of the shift register is connected to the contact inputs of the first and second elements And, and the first output of the shift register is connected to the second input second signal processing unit. FIG. 1 shows the functional electrical circuit of the demodulator in FIG. 2 - stress diagrams for his work. The demodulator of the frequency and phase signals of telegraphy contains a limiter-shaper 1, a register 2 shifts, a first signal processing unit 3, a second signal processing unit 4, inverters 5 and b, the first element And 7, the second element And 8, and a filter 9 manipulation. The device works as follows. The input signal is fed to the limiter driver 1, is converted into square-shaped pulses, the frequency of which corresponds to the frequency of pressing or pressing (Fig.. 2a). Rectangular pulses are applied to the shift register 2, in which they are delayed by the time t-N / f, where N. is the number of bits of the shift register 2; - clocking frequency. Then, at the first output of the shift register 2, the output signal (Fig. 2cH) will be delayed by time t, -tt / 8, and at the second output (Fig. 26) - by the time, where t., - 1 / fc. - the period of oscillation of the average frequency of the spectrum. Thus, the first signal processing unit 3 receives a signal from, the first output of the shift register 2 and leading it by time / 8 signal from the output of the limiter maker 1. The second signal processing unit 4 receives a signal from the main output of the shift register 2 and the signal is lagging from him for the time tz-r,. In this case, the outputs of the blocks 3 and 4 of the signal processing are voltage logical unequalities (Fig. 2 2.9) - The signals from the outputs of the blocks 3 and 4 of the signal processing go directly to the inputs of the first element And 7, and through inverters 5 and 6 - to The inputs of the second element And 8. At the clock inputs of the elements 7 and 8, the clocking frequency is also set (Fig. 2e). Such a cross-connect allows to obtain O levels at the output of the first element And 7 (Fig. 2 "n) at the input signal frequency corresponding to pressing, and At the output of the second element 8 - levels (Fig. 2h) at the frequency of the input signal corresponding to release. From the outputs of both elements, And 7 and 8, the signals arrive at the input of the digital filter 9 manipulation. The inputs to the digital filter 9. manipulation signals are integrated. The displacement at the output of the digital filter 9 of the manipulation is formed as a binary number, the level of which determines the received elementary parcel, i.e. determines its appearance (Fig. 2k). When digital filter 9 is executed, the manipulation in the form of a reversible counter and triggers is performed as follows. When pulses arrive, for example, from the output of the first element I 7 to the input of the filter 9, the manipulation and, therefore, to the summing input of the counter, the last one is filled with passing pulses and, when filled, does not change its

state, which is achieved due to the control scheme of the triggers, and at the same time the output signal is generated by the level corresponding to pressing. If the pulses come from the output of the second element AND 8 to the input of the filter 9, manipulation, which means to the subtraction input of the counter, this counter begins to work for subtraction and when fully zeroed by three, the level O is formed, which corresponds to release. Solitary

the pulses arriving from the outputs of the And 7 and 8 elements do not change the output signal, since the capacity of the counter is chosen sufficiently large. The capacity of the counter is determined by the clocking frequency and the sending time of the received signal.

The invention improves the noise immunity by reducing the telegraph distortion of the type of dominance (marginal distortion).

pppppppy

YUSHSHSHSHSHSHSH

shshshshshshshshshsh

1111 IHItlllliimilllHIII Illlli

3

I / s

GSHSHG

ishsh

II HlllllllUHliHillimiHHIi tires II

nor 111 Illlimilt

one

Claims (1)

DEM SIGNAL FREQUENCY AND PHASE TELEGRAPH comprising sequentially (connected limiter-generator, shift register and the first signal processing unit, a second input coupled to an output limiter-shaper, while the second output of translations _register; n is connected to the first input of the second signal processing unit, and a manipulation filter, characterized in that, in order to increase the noise immunity, two inverters and two And elements are introduced, and the outputs of the first and second signal processing units are connected to the inputs of the first AND element directly and to the inputs of the second AND element through inverters, the outputs of the AND elements are connected to the corresponding inputs of the manipulation filter, which is digital, the second input of the shift register is connected to the clock inputs of the first and second elements AND, and the first output of the shift register is connected to the second the input of the second signal processing unit. SU .... 1070683