SU1378082A1 - Transceiver of discrete information - Google Patents

Abstract

. This invention relates to telecommunications and increases transmission speeds. The device contains transmitter 1, communication channel 2, input amplifier 3, synchronizer 4, multiplier 6, integrators 7, r-10 frequency grid, counter 12, storage unit t3, unit 14 for calculating phase difference, solving unit 15. Again introduced a multi-pole tunable notch filter 5 and switches 8 and 9. Filter 5 consists of an amplifier, a tunable rejection filter, a delay unit and an adder. 1 hp f-ly, 2 ill.

Description

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The invention relates to telecommunications and can be used to transmit data with phase modulated signals.

The purpose of the invention is to increase the transmission speed.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 is a structural electrical circuit of a multi-pole tunable notch filter.

The device for transmitting and receiving discrete information contains transmitter 1, communication channel 2, input amplifier 3, synchronizer 4, multi-pillar tunable notch filter (MPRF) 5, multiplier 6, integrators 7, switches 8 and 9, frequency grid generator 10, a clock pulse generator 11, a counter 12, a storage unit 13, a phase difference calculation unit 14, a decision block 15.

The multi-pole tunable notch filter 5 consists of an amplifier 16, a tunable notch filter 17, a delay unit 18 and an adder 19.

The device works as follows ..

The disc arriving at transmitter 1 is distributed over channels; 1 lam, each of which carries discrete phase modulation of carriers with frequencies Kd-F (K is an integer and 4F is a frequency interval between carriers). The modulated carriers are added up and transmitted over link 2.

In the receiver, using the input amplifier 3, the signal level is set for the normal operation of the subsequent units. The group signal from the output of the input amplifier 3 is fed to the MPRF 5 to separate the channel carriers. The selected carrier values of each channel follow one another cyclically successively in time. The phase difference between the received and reference signals is calculated using correlators, the multiplication of the signals for each channel is performed by a common multiplier 6, and the integration in the channels is performed by the corresponding Sch1F1I integrators 7. For this, the clock generator 11 generates pulses

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much less than the duration of a single element of the signal. These pulses cyclically change the state of the counter 12, the signals of which simultaneously change the state of the MPRF 5 and the switches 8 and 9. Moreover, if at the next clock interval from the MPRF 5 to one input of the multiplier 6, the signal of the channel with the number i, To the second input of the switch 9 connects the reference signal with the same number i, and the signal from the output of multiplier 6 is supplied by the switch 8 to the integrator 7 with the same number 1. At the next clock interval, the counter code is increased by 1, the state of the MSRF 5 changes and switches 8 and 9, 6 are supplied to the multiplier signals vzdel emogo next channel and the reference waveform. At the same time, the switch 8 connects the next integrator 7 to the output of the multiplier 6. Thus, this process is repeated cyclically many times over the duration of a single signal element, at the end of which the voltage values from the outputs of the integrators 7 are written to the storage unit 13 by signals from synchronizer 4. The voltages obtained during the processing of two adjacent single elements of the signal and recorded in the storage unit 13 are fed to the block 14 for calculating the phase difference for the relative decoded signal and According to the results of calculations of block 14, decisive block 15 decides on the transmitted symbols and enters the received information sequence to the recipient. MPRF 5 works as follows. The input signal is fed to the inputs of the adder 19 and the amplifier 16, which forms together with the tunable notch filter 17 included in the positive feedback circuit 17 and the delay unit 18 a comb filter. At selection frequencies of the comb filter K21I / T (where K is 1,2,3 ..., s and T is the delay time), signals to the inputs of the adder 19 are received in antiphase and with the transfer coefficient of the comb filter equal to one, the output voltage of the adder 19 at these frequencies is almost zero. At other frequencies, the phase relations between the signals at the input of the adder 19 change and at its output there is a nonzero result.

tat summation. At the tuning frequency of the tunable notch filter 17, a positive attenuation is introduced into the positive feedback circuit of the amplifier 16, which eliminates the selection of the comb filter at this frequency. In this case, the signals at the inputs of the adder 19 have different amplitudes, and this allows the oscillation of only one frequency to be isolated from the group signal.

Claims (1)

1. An apparatus for transmitting and receiving discrete information comprising a serially connected transmitter, a communication channel, an input amplifier and a synchronizer, the second input of which is connected to the first output of a frequency grid generator, a multiplier, serially connected storage unit, a phase difference calculator and a decision unit , the first inputs of which are connected respectively to the first, second and third outputs of the synchronizer, the fourth output of which is connected to the first inputs of the integrators, the outputs of which are connected to co sponds to the inputs of the storage unit, characterized in that, in order to increase the transmission rate, two switches are administered serially connected generator clock pulses and a multi-pole tunable notch filter, the second input of which is connected to the output of the input amplifier, the output of which is connected to the first input of the multiplier, the output of which is connected to the first input of the first switch, the outputs of which are connected to the second inputs of integrators, the output of the counter is connected to the second input of the first switch and the first input of the second switch, the other inputs and output of which are connected respectively to the outputs of the frequency grid generator and the second input of the multiplier, 2, the device according to claim 1, characterized in that the multi-pole tunable notch filter consists of an amplifier, a delay unit, a tunable notch filter and an adder, the output of the amplifier through a serially connected tunable notch filter and a delay unit is connected to the first input of the amplifier, vpsod which is connected to the first input of the adder, the second input of which and the second input of the amplifier are combined and are the second input of a multi-pole tunable notch filter, the first input of which is a second tunable notch filter input and output - the output of the adder.