SU1223385A1 - Communication system with multibase coding - Google Patents

Abstract

The invention relates to communication technology, to information transmission systems with limited frequency and energy potentials. The rate of information transfer increases. The system contains, on the transmitting side, a signal source, a differential encoding unit, a signal converter, a switching sequence driver, a carrier frequency generator, a phase shift control unit, a phase modulator, a power amplifier, a clock generator, a frequency divider, and a separate differential coding unit (BRDK). On the receiving side, a preamplifier and a selection unit, a multichannel correlator, a maximum signal selection unit, two decoders, a code pattern recovery unit, a carrier frequency recovery unit, a reference driver, a synchronization unit, a signal receiver, a separate relative decoding unit (BROD) . The rate is increased by introducing at the front of the BRDC, and at the receiving part of the BROD. 2 Il. 9 th tc from 00 ate

Description

The invention relates to communication technology, namely to information transmission systems. With limited frequency and power potential.

The purpose of the invention is to increase the speed of information transmission.

FIG. 1 shows a structural electrical circuit of a transmission part of a multi-core coding communication system; in fig. 2 is a structural electrical circuit of the receiving part of the communication system # 1 with multi-core coding.

The multibasic coding communication system contains a source of I signals, a differential coding unit 2, a converter of 3 signals, a shaper of 4 switching sequences, a carrier frequency generator 5, a phase shift control unit 6, a phase modulator 7, a power amplifier 8, a generator 9. clock pulses, frequency divider 10, unit 11 of the separate differential coding, preamplifier and selection unit 12, multichannel correlator 13, maximum signal selection unit 14, first decoder 15, code combination recovery unit 16, carrier frequency recovery unit 17, driver 18 reference signals, second decoder 19, synchronization unit 20, signal receiver 21, separate relative decoding unit 22.

A multi-core coding communication system operates as follows.

The sequence of binary signals (Fig. 1) from the output of the source

The signals enter block 2 of differential coding and block

I1 is a split differential encoding. In block 2 of the differential encoding, the binary data is converted into a new sequence of binary symbols of the interdependent type. This sequence of characters enters the converter of 3 signals. From the output of the converter of 3 signals (in a parallel code) this binary signal enters the shaper of switching sequences, to another input of which impulses come from the output of frequency divider 10.

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formed from clock frequency E) by dividing it by four. Formed The 4 switching sequences analyzer analyzes four5 bit combinations, if an odd type combination (by the number of ones or zeros) is received, then the output signal of the 4 switching sequences generates a signal Ocht,

which enters unit 2 of separate differential encoding. From the Optical signal, switching commutator sequences corresponding to a carrier oscillation of the coscOjt type and. These switching sequences are used to control shear.

20 of the phase of the carrier oscillation and for dividing the initial data stream, which is input to the block 11 of the separate differential encoding. In block 11 of the differential differential coding, a delay of a sequence of binary symbols is performed, an output from the output of the source 1 signals, a delay is necessary for - matching the signals

2 lines from the output of the 4 KOtf generator of mutating sequences with the information sequence of binary symbols, since in the converter of 3 signals the transformed sequence of characters is delayed by four clock cycles. Then the delayed sequence of binary symbols in block 11 of the separate differential encoding is divided into two sequences using switching sequences, followed by encoding the information symbols using the relative (differential) method separately on two identical channels. The resulting two sequences are summed into one sequence of binary symbols. Moreover, this sequence consists of a set of 16 four-bit combination

5 tions: 8 even type combinations and 8 odd type combinations. The signal of the feature Odd, delayed by three cycles, converts odd four-bit combinations into even ones by inverting the fourth bit of the odd combinations. Thus, at the output of the block about 11 separate differential

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a coding sequence is formed of binary SIMULUSES consisting of a set of 8 biorthogonal even four-bit combinations corresponding to a carrier oscillation type cos Wo t and sin code t. These output signals in the phase modulator

7, a phase modulation of the Hecyniero oscillation is performed, which has undergone additional processing in the phase shift control unit 6. The resulting signal is amplified in an amplifier.

8 and is fed into the communications line to the receiving side.

At the receiving side (Fig. 2), the incoming signal is first fed to the preamplifier 12 and. selection. Then, from the received signal in block I7 of carrier frequency recovery and synchronization block 20, the synchro parameters — carrier frequency, clock frequency of binary symbols and cycle frequency of the sequence of combinations — are separated. On the basis of the allocated carrier, clock, and cycle frequencies, reference signal generator 1B is used to generate copies of the transmitted signals (reference oscillations), which are fed to the information extraction channel. The main element of this channel is a multichannel correlator 13, which calculates the convolutions of the received signal with all copies (integration time, where Tg is the time allotted for transmitting each bit) and the results of calculating the correlation integrals at times, where, 2, ..., the number of which naturally coincides with the number of different signals, is supplied to the parallel inputs of the block 14 and the first selection of the maximum signal. At the bottom of the outputs of block 14, a normalized signal is formed, a fixed channel number, at the output of which the received signal gives the maximum output effect. The signals from the outputs of the maximum signal selection unit 14 are fed to the first decoder 15 and the second decoder 19. The task of the first decoder 15 is the reformation of the normalized pulse signal at the output of the block 14 into the corresponding four output (even type combination). The second decoder 19 is based on the analysis of the

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The scientific research institutes accepted at the current and previous intervals determine whether these solutions are of the same type of carrier (sinOgt or cos) or non-existent of different types (sinco t and cosui t or coscOgt and sincOjjt), and forms this basis, at its output, the sign (impulse) of the membership of the current combination to the

to the odd type, as well as the switching sequences, which arrive at the corresponding inputs of the separate relative decoding unit 22. No impulse on

15 output of the second decoder 19 corresponds to the reception of a combination of even type.

At the final stage of processing in block 16, the recovery code 1x

2Q combinations based on the output of: the signals of the first decoder 15 and the second decoder 19, a reconstructed pattern is formed, which in the sequential code arrives

5 to the input of a separate relative decoding unit 22, where this sequence of binary symbols is divided into two using commuting

Q sequences dp separate decoding and final reproduction of the received binary information followed by its output to the receiver 21 signals.

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Claims (1)

Invention Formula A multi-core coding communication system that contains a serially connected signal source, a differential encoding unit, a signal converter and a switching sequence generator, a series-connected carrier frequency generator, a phase shift truncating unit, a phase modulator and a power amplifier, and a clock pulse generator on the transmitter side. and a frequency divider, with the output of the signal source connected to the input of the clock pulse generator, the output of which is connected to the control The main inputs of the differential encoding unit, the signal converter and the frequency divider, the output of the frequency divider are connected to the control input of the driver The switching sequences, the information outputs of which are connected respectively to the information inputs of the phase shift control unit, on the receiving side, the system contains a series-connected preliminary amplification and selection unit, a multichannel correlator, and a selection unit maximally. signal, the first decoder and the recovery unit code combinations, as well as the recovery unit carrier frequency, the driver of the reference signals, the second decoder, synchronization unit and receiver of signals, the input of the recovery unit of the carrier frequency connected to the output of the preamplifier and selection unit and the first input the synchronization unit, the first output of which is connected to the control inputs of the multichannel correlator, the maximum signal selection unit, the first decoder, the second decoder, and the first controller The reference signal generator vhbdom, the second output of the synchronization unit is connected to the second control input of the reference signal conditioner and the first control input of the code combination recovery unit, the first and second outputs of the carrier recovery unit are respectively connected to the third control input of the reference signal conditioner and the second input block synchronization, the output of the driver reference signals connected to the second input mnogoFig. one 0 the channel correlator, and the output of the maximum signal selection block is connected to the information input of the second decoder, the output of which is connected to the second control input of the code combination recovery block, which is so that, in order to increase the information transfer rate, a separate block is entered on the transmitting side differential coding, the signal input of which is connected to the output of the driver of the switching sequences, the direct and 5 inverse outputs of which are connected respectively to the switching by their inputs of a separate differential encoding unit, whose information input is connected to the output of a signal source, the output of a clock generator is connected to a synchronizing input of a separate differential encoding unit, the output of which is connected to a second input of a phase modulator, a separate relative decoding unit is inserted at the receiving side, the output of which connected to the input of the receiver signals, and the output of the block recovery code combinations connected to the information input of the block nogo relative decoding control, the first and second switching inputs of which are respectively connected to the second output of the synchronization unit, the first and second complementary outputs of the second decoder. 0 five 0 d fig z