SU1533013A1 - Discrete information transmission system - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the transmission speed. The system contains a synchronizing generator 1, a coding unit 2, a signal generator 3 and a transmission filter 4 on the transmitting side, and a receiving filter 5, a signal regenerator 6, a synchronization unit 7 and a decoding unit 8 on the receiving side. The system signal transmitted to the communication channel, when using a multiple bi-pulse code, occupies a much smaller frequency band than in the prototype. Examples of the execution of the encoding and decoding units 2 and 8 are given. 1 Il.

Description

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The invention relates to the field of telecommunications and can be imported - but for transmitting binary signals via cable lines and U-band radio channels.

The purpose of the invention is to increase the transmission speed.

The drawing shows a structural electrical circuit of a discrete information transmission system.

The system for transmitting discrete information contains on the transmitting side a synchronous generator 1, a coding unit 2, a signal generator 3 and a transmission filter C, and on the receiving side a receiving filter 5, a signal regenerator 6, a synchronization unit 7 and a decoding unit 8, while the coding unit 2 includes a delay unit 9, a decryptor of 10 tribits, an element of NOT 11, the first is the sixth dividers 12 is 17 frequencies into two, the first is the eighth element AND 18 is 25 and the element OR 26, and the decoding unit 8 includes the first element And 27, the first delay element 28, second element, 29, second ement delay 30, third AND gate 31P third delay element 32, the EX-OR element 33, the fourth delay element 3, the OR gate 35 and the fourth AND gate 36.

The system of transmission of discrete information works as follows.

The information sequence to be transmitted enters through the information input to the input of coding unit 2. Using the clock sequence generated by the synchronizer 1, the delay unit 9 converts the incoming information sequence into a parallel form — tritits. Depending on the value of the symbols of each three-bit at the corresponding output of the decoder 10, the tribit is a control pulse of three clock intervals of information accuracy.

From the other sync-loop 1, a synchronous sequence arrives, which is in the ratio of V3 to the clock frequency of the information sequence. This clock sequence is fed to the input of the fourth divider 15 frequency by two and through the element NOT 11 to the input of the first divider 12 frequency by two.

After further division of the h-ji gy with the help of the second, third i ch-.i (... and the sixth dividers P, 1, and I / frequencies into two received direct and inverse sequences arrive at the first inputs of the first - eighth elements And 18 - 25, respectively. When each tribit arrives, the control signal from the corresponding output of the decoder of 10 tribits turns out to be open one of the eight AND elements, the signals from the outputs of which are summed with the help of the OR element 26.

In the proposed system, eight source tribits are converted into triple bi-pulse signals in accordance with the following rule:

Source Tribit Output Signal

00001111 00011110 01 111000 00111100 10000111 11000011 11110000 11100001

The signal from the output of the coding unit 2 through the driver 3 of the signal and the transmission filter k is fed to the output of the system and then to the communication channel.

At the receiving side, the incoming signal after filtering in the receiving filter 5 is regenerated by the signal regenerator 6 and is fed to the input of the decoding unit 8. The block / synchronization performs the clock and block synchronization, which is necessary for decoding. The property of the received signal is used in that the second half of the received words is the exact logical inversion of their first half.

The decoding process of a three-time bi-pulse code (8-bit words) into source tribits occurs according to the following rule:

a, b i where a

 3

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B - b.

the first is the third character of the resulting tribit, respectively; character values of the first to fourth bits of the 8-bit word being received;

@ - modulo two summation.

The control signals from block 7 sync grise through alternate opening of the first, second, third and fourth elements And 27,29,31 and 36 when the first, second, third and fourth characters of the received word arrive. The EXCLUSIVE OR 33 element performs the modulo two sum operation. The delay of the second delay element 30 is two clock intervals of the frequency of the incoming signal. Using the first, third, and fourth delay elements 28, 32, and 3, the required arrangement of the symbols of the resulting tribit is performed in time. Tribit symbols are summed by AND 35.

The signal transmitted to the communication channel, when using a multiple bi-pulse code, occupies a much smaller frequency band than in the prototype, which ensures an increase in the transmission rate.

invention formula

A discrete information transmission system comprising a clock generator and a serially connected coding block, a signal conditioner and a transmission filter whose output is the output of the system whose information input is the information input of the coding block, and a serially connected receiving filter and regenerator on the receiving side the signal, the synchronization unit and the decoding unit, the output of which is the information output of the system, whose input is the input of the receiving filter, the output of which is connected to the input of the synchronization unit, and the output of the signal regenerator is connected to the information input of the decoding unit, characterized in that, in order to increase the transmission speed, on the transmitting side the first and second control inputs of the encoding unit are connected to the corresponding outputs of the clock generator, and on the receiving side, the outputs of the synchronization unit are connected to the corresponding signal inputs of the decoding unit

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the coding block consists of a serially connected delay block and a triple decoder, a NOT element, six frequency dividers for two, eight AND elements and an OR element whose output is the output of the coding block whose information and first and second control inputs are respectively the information and clock inputs of the delay unit and the input element NOT, the output of which is connected to the input of the first frequency divider into two, the direct and inverse outputs of which are connected to the inputs of the second and third dividers h Frequencies for two, direct and inverse outputs of which are connected to the first inputs of the first, second, third and fourth elements I, and the direct and inverse outputs of the fourth frequency divider by two are connected to the inputs of the fifth and sixth frequency dividers by two, direct and the inverse outputs of which are connected to the first inputs of the fifth, sixth, seventh and eighth And elements, the second inputs of which and the second inputs of the first, second, third and fourth elements And are connected to the corresponding outputs of the triple decoder, and the outputs

the first to the eighth And elements and the input of the fourth frequency divider by two are connected to the inputs of the OR element and the input of the NOT element, while the decoding unit consists of the first And elements and the delay element, the second And elements and the delay element, and the third elements sequentially connected And and the delay element connected in series the EXCLUSIVE OR element and the fourth delay element, the OR element and the fourth AND element, the output of which and the output of the second delay element ki are connected to the inputs of the EXCLUSIVE OR element, and the inputs of the OR element are connected to the outputs of the first, third and fourth delay elements, the first inputs of the first, second, third and fourth elements I are connected to the information input 55 of the decoding unit, the output and signal inputs of which are the output of the OR element and the second inputs of the first, second, third, and fourth elements I.

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Claims (1)

Claim A discrete information transmission system comprising a sync generator on the transmitting side and (a coding unit, a signal conditioner and a transmission filter connected in series, the output of which is the output of the system, the information input of which is the information input of the coding unit, and on the receiving side, a receiving filter and a signal regenerator , a synchronization unit and a decoding unit, the output of which is the information output of the system, the input of which is the input of the receive filter, which is connected to the input of the synchronization unit, and the output of the signal regenerator is connected to the information input of the decoding unit, characterized in that, in order to increase the transmission speed, on the transmitting side, the first and second control inputs of the encoding unit are connected to the corresponding outputs of the clock generator, and on the receiving side the outputs of the synchronization unit are connected to the corresponding signal inputs of the decoding unit. the inputs of the fifth, sixth, seventh and eighth elements And, the second inputs of which and the second inputs of the first, second, third and fourth elements 3Q And are connected to the corresponding outputs of the decoder tribits, and the outputs of the first - the eighth elements And and the input of the fourth frequency divider are connected to two the inputs of the OR element and 35 the input of the element NOT, wherein the decoding unit consists of series-connected first elements AND and a delay element, series-connected second elements AND and a delay element connected in series of the third AND element and the delay element, the EXCLUSIVE OR element connected in series and the fourth delay element, the element 45 '~, the OR element and the fourth AND element, the output of which and the output of the second delay element are connected to the inputs of the EXCLUSIVE OR element, and the inputs of the OR element are connected to the outputs of the first, third, and fourth delay elements, the first inputs of the first, second, third, and fourth AND elements are connected to the information input of the decoding unit, the output and signal inputs of which are etstvenno output of the OR gate and the second inputs of the first, second, third and fourth elements I.