RU2249919C2 - Receiver for discontinuous data with automatic synchronization of transmission speeds - Google Patents

Abstract

FIELD: communications.

SUBSTANCE: if signal length is changed in more than two times in communication line, block for detecting mismatch of speeds generates pulses, which are sent to input of reverse counter being part of speed code generation block, which counts number of distortions on given time range with consideration of sign of speed mismatch and in case of overflow generates new speed code, which at the end provides for receiving of clock frequency of transmission, matching speed of signals, sent to data input of device.

EFFECT: higher efficiency.

2 cl, 3 dwg

Description

The invention relates to communication technology and can be used in the development of equipment for the transmission of digital information represented by two-interval BI, FM and FM channel codes.

Known receivers dvuhintervalnyh channel codes generated using only two time intervals: τ ₀ and τ _0/2, where τ ₀ - duration of a single data signal, equal to the clock interval. The most widely used are phase-shifted (FM) or Manchester code (GOST 26765.52-87), bi-pulse (BI) code (GOST 27232-87) and frequency-manipulated (FM) code.

Such devices include, for example, “Decoder” [1], which performs the formation of the clock frequency of reception and decoding of the information represented by two-channel channel codes. The disadvantages of the device are the cessation of the formation of the clock frequency during fading of the signal in the communication lines and, as a result, a failure of the cyclic synchronization of the data transmission equipment, as well as operation at only one speed.

The “Synchronization and decoding device” [2] is deprived of these drawbacks, which provides automatic tuning and the formation of the clock frequency of reception (including during fading of signals in the communication line), as well as decoding of signals of two-channel channel codes. The disadvantage of this device is the mandatory participation of staff to change the speed of data exchange. This requires a significant investment of time in the formation, transmission and reception of the corresponding message, which reduces the performance of the communication line.

Closest to the proposed technical solution is the “Digital Information Receiver” [3], selected for the prototype, which automatically generates a code for the speed of the device.

Figure 1 presents the functional diagram of the device of the prototype. The device comprises a master oscillator 1, a reference frequency driver 2, a signal analyzer 3, a frequency generator 4, a decoder 5, a first 6 and a second 7 D-flip-flops, an AND 8 element, an OR 9 element and a binary counter 10, as well as an information 11 controlling 12 and installation 13 inputs, clock 14 and information 15 outputs.

The device has the following connections. The output of the master oscillator 1 through the reference frequency driver 2 is connected to the first inputs of the signal analyzer 3, the frequency driver 4 and the decoder 5. The output of the decoder 5 is connected to the information output 15 of the device, the information input 11 of which is connected to the second input of the signal analyzer 3. The first output of the last connected to the second input of the decoder 5, and the second to the second input of the shaper 4, the first output of which is connected to the clock output 14 of the device and to the third input of the decoder 5, the second to the fourth at the input of the decoder, the third and fourth - to the information inputs of the first 6 and second 7 D-flip-flops, respectively, the fifth - to the clock inputs of the first 6 and second 7 D-flip-flops and to the first input of the OR element 9. Direct output of the first 6 D-flip-flop and the inverse output of the second 7 D-flip-flop connected to the inputs of the AND 8 element, the output of which is connected to the second input of the OR element 9, connected by the output to the counting input of the binary counter 10, the input of which is set to “0” and connected to the installation input 13 of the device, and the output to the second input of the reference driver frequency 2. The control 12 input of the device is connected to the combined third input of the driver 4 clock frequency and the fifth input of the decoder 5.

The known device operates as follows. The information input 11 of the device receives data encoded by one of three two-channel channel codes (BI, FM, FM). On the control input 12 of the device is fed a log. “0”, if the data coming from the communication line is encoded by BI and FM with two-interval codes, and a log. “1” if the data is encoded by the FM two-interval code.

The signal analyzer 3 is the selection of the fronts and decays of the signals of the encoded sequence received at the information input 11 of the device. Each of these pulses is initialized to counter 4.1 of the clock frequency generator 4. The counter performs the function of an integrator, which, together with the allocation of the correction pulse (elements 4.2 and 4.3), adjusts the phase of the divider by 2, performed on the D-trigger 4.4, which forms the clock frequency of reception. When encoding data with a BI code, correction pulses are generated at each transition of the original signal from “1” to “0”, when encoding with an FM code — at every “0” in the original signal, when encoding with an FM code — at each transition of the original signal from “1” to “0” and from “0” to “1”. Correction pulses provide confirmation or restoration of common mode. The corrected frequency is supplied to decoder 5. The latter contains a scheme for extracting “units” of the original sequence from encoded signals, performed on elements 5.1-5.6, as well as switch 5.8 and D - trigger 5.7. When decoding BI and FM codes, the output of switch 5.8 under the action of a control signal receives signals from the output of element 5.6 of the “units” allocation circuit. At the same time, through the switch 4.5, the frequency from the inverse output of the D-trigger 4.4 is output to the clock input of the D-trigger 5.7, which ensures the presence of the receive clock and the common-mode decoded data on the clock 14 and information 15 outputs of the device. The foregoing is explained in detail in the timing diagrams shown in figure 2, 3 and 4 in [2].

The adjustment to the required speed is as follows. A signal is set to the installation 13 input of the device, setting the binary counter 10 to the “0” state, which corresponds to the maximum reference frequency being connected to the output of the multiplexer 2.2, as a result of which the counter 4.1 of the clock frequency shaper 4 is overflowed in its additional discharge (2 ^{m + 1} ) “1” appears. When the next correction pulse of the state of the highest (2 ^m ) and additional (2 ^{m + l} ) bits of the counter 4.1 appears at the output of element 4.2, they are fixed by D-flip-flops 6 and 7, while the state “1” at the direct outputs of these triggers indicates the need to lower the value reference frequency and at the output of element And 8 appears the log. “0”, allowing the passage of correction pulses to the counting input of the binary counter 10. For each pulse, the counter receives an increment of the code generated by it by one. The process continues until the D-flip-flops 6 and 7 fix the state “1” and “0”, respectively, which is accompanied by the formation of an And 8 log element at the output. “1”, blocking the passage through the element OR of 9 correction pulses to the counting input of the binary counter 10. As a result, the value of the reference frequency does not change in the future, which indicates the completion of the process of adaptation of the device to the speed of signals coming from the communication line.

From the description of the operation of the prototype device, it follows that it provides automatic adjustment of the speed of the signals coming from the communication line if it is lower than the speed of the receiver. Otherwise, it is necessary to generate an external installation signal supplied to the installation 13 input of the device. This is possible either manually by the operator, or, for example, by counting errors in the received signal at a given interval, etc., which requires time and reduces the performance of the communication line.

In addition, in the known device, a clock synchronization failure may occur under the influence of interference, causing distortion of the signal duration by 2 or more times in one direction or another. In fact, according to regulatory documents on two-interval codes (GOST 26765.52-87, GOST 27232-87), their speed changes with a multiplicity factor of two, therefore, the effect of this kind of interference is perceived by a known device as a change in transmission speed. Thus, despite the equality of the transmission and reception rates, due to the influence of this kind of interference, there is a mismatch between the transmission and reception speeds, i.e. violation of clock, and after this and cyclic synchronization. This leads to loss of information for the time required for a new entry into the clock and cycle synchronism, which ultimately reduces the performance of the communication line.

The objective of the proposed device is to increase the performance of the communication line.

The technical result achieved by the proposed device is to automatically determine the sign of the mismatch of the speeds of the transmitting and receiving sides and bringing them into conformity by developing a reference frequency that provides receiving clock frequency corresponding to the value of the speed of incoming information. At the same time, an additional technical result is achieved, which consists in eliminating the false determination of the mismatch of transmission and reception speeds when the quality of the communication channel matches the selected criterion — the allowable number of signal duration distortions over a given time interval.

The specified technical result is achieved by the fact that in the receiver of discrete information with automatic matching of transmission and reception speeds, containing a master oscillator, a reference frequency driver, a signal analyzer, a clock frequency generator, a decoder, an AND element, a time interval counter, an OR element connected to a counted output the input of the counter of the time interval, the control and information inputs, the clock and information outputs, while the output of the master oscillator through the driver of the reference frequency connected to the first inputs of the signal analyzer, clock generator and decoder, the output of which is connected to the information output of the device, the information input of which is connected to the second input of the signal analyzer, the first output of which is connected to the second input of the decoder, and the second to the second input of the clock frequency, the first output of which is connected to the clock output of the device and to the third input of the decoder, the second to the fourth input of the decoder, the fifth input of which is combined with the third input of the clock generator howling frequency and connected to control input devices, introduced mismatch determination unit velocity generating unit code rate, code rate storage unit and the RS-flip-flop. In this case, the output of the reference frequency driver and the output of the master oscillator are additionally connected respectively to the first and second inputs of the speed mismatch determination unit, the third, fourth, and fifth inputs of which are connected respectively to the third, fourth and fifth outputs of the clock frequency driver, the sixth is connected to the second output of the signal analyzer and the first and second outputs, respectively, to the counting and control inputs of the speed code generation unit, executed on a reversible counter, the outputs of which th connected to the control input of the reference frequency. The output of the overflow signal of the reverse counter of the speed code generation unit is connected to the installation input in “1” of the RS flip-flop, the output of which is connected to the second input of the AND element, the output of which is connected to the control input of the speed code memory block, and the first input is combined with the first input of the OR element and connected to the second output of the signal analyzer. The setup input at “0” of the time interval counter is connected to the first output of the speed mismatch determination unit, and the output is connected to the second input of the OR element, to the high-order blocking input of the reverse counter of the speed code generation unit, and to the setup input to the “0” RS trigger.

The essence of the proposed technical solution is to determine the mismatch of transmission and reception speeds by counting alternating signs at a given time interval. At the same time, the decision on the presence of a mismatch in the transmission and reception rates is made not for each case of distortion of the signal duration by 2 or more times, as is the case in the prototype, but according to the given value of the predominance of distortions of one sign (increase or decrease in duration by 2 or more times) on the time interval determined by the division ratio of the counter of the time interval. Moreover, since the speed code generation unit calculates the average value of distortions of different signs that occur during random changes in the signal duration under the influence of noise in the communication line, the probability of overflow of the reverse counter of the speed code generation unit and the generation of a false speed mismatch signal over a time interval specified with given the quality of the communication channel is extremely small.

When the transmitter switches to a different operating speed and there is a duration distortion under the influence of interference (or in the absence thereof), the predominance of distortions of one sign becomes stable, which leads to the formation of a speed mismatch signal in the form of “1” at the additional output of the speed code generation unit and provides speed adjustment reception to the transmission rate.

Figure 1 shows the functional diagram of the device of the prototype.

Figure 2 presents the functional diagram of the proposed device.

Figure 3 shows the functional diagram of the unit for determining the mismatch of speeds.

The proposed device (figure 2) contains a master oscillator 1, a driver of the reference 2 frequencies, a signal analyzer 3, a driver of a clock 4 frequencies, a decoder 5, a unit for determining a mismatch of speeds (BORS) 6, a unit for generating a speed code (BFKS) 7, a code memory unit speed (BPKS) 8, the element OR 9, the counter of the time interval 10, the RS-trigger 11, the element And 12, the information input 13 and output 14, the control 15 input and clock output 16.

The device has the following connections.

The output of the master oscillator 1 through the driver of the reference 2 frequencies is connected to the first inputs of the signal analyzer 3, the unit for determining the mismatch of speeds 6, the driver of the clock 4 frequencies and decoder 5. The output of the decoder 5 is connected to the information output 14 of the device, the information input 13 of which is connected to the second input of the analyzer signals 3, the first output of which is connected to the second input of the decoder 5, and the second - with the first inputs of the element And 12 and the element OR 9 and the second inputs of the unit for determining the mismatch of speeds 6 and form 4 ovatelya clock frequency, whose first output is connected to the clock output unit 16 and to the third input of the decoder 5, the second - fourth input to the decoder 5, the fifth input of which is combined with a third input of the clock frequency 4 and connected to the control input 15 of the device. The third, fourth and fifth outputs of the frequency 4 clock driver are connected respectively to the third, fourth and fifth inputs of the speed mismatch determination unit 6, the sixth input of which is connected to the output of the master oscillator 1. The first output of the speed mismatch determination unit 6 is connected to the installation input to “0” the counter of the time interval 10 and the counting input of the block forming the speed code 7, made on the reverse counter, the control input of which is connected to the second output of the block for determining the differences 6. Outputs of velocities reversible code block formation speed counter 7 connected to data inputs of the storage unit code rate of 8, the outputs of which are connected to the control input of the reference frequency 2. The output of the overflow signal of the reverse counter of the speed code generation unit 7 is connected to the installation input in “1” of the RS flip-flop 11, the output of which is connected to the second input of the And 12 element, connected to the control input of the speed code memory unit 8. The output of the time interval counter 10 is connected to the installation input to “0” of the RS-flip-flop 11, to the high-order blocking input of the reverse counter of the speed code generation unit 7 and to the second input of the OR element 9, the output of which is connected to the counting input of the time interval counter Ala 10.

Examples of implementations of a frequency reference driver 2, a signal analyzer 3, a frequency driver 4, and a decoder 5 are shown in FIG.

The unit for generating the speed code 7 can be implemented, for example, on a reversible counter containing the lower 7.1 and senior 7.2 bits (Fig. 2), while the control and counting inputs of the reverse counter are respectively control and counting inputs, and the outputs of the lower digits of the reverse counter are the outputs of the block forming the speed code 7. The inputs of the setting to “0” high bits and the output of the last high bit of the reversible counter are respectively the input blocking high bits and the output of the overflow signal bl oka speed code formation 7.

The memory block of speed code 8 can be executed, for example, on D-flip-flops 8.0 ... 8.i, while the information and synchronizing inputs of D-flip-flops are respectively the information and control inputs of the memory block of speed code 8, and the outputs of D-flip-flops are outputs of said memory block.

An example implementation of the unit for determining the mismatch of speeds 6 is shown in figure 3. BORS 6 contains a binary counter 6.1, shift register 6.2, first 6.3 and second 6.4 elements OR, first 6.5, second 6.6 and third 6.7 elements AND, element NAND 6.8, element OR NOT 6.9, first 6.10, second 6.11, third 6.12 , fourth 6.13, fifth 6.14 and sixth 6.15 D-triggers. BORS 6 has the following connections. The first input of BORS 6 is connected to the first input of the first element OR 6.3, the second to the combined first input of the first element AND 6.5 and the clock input of the shift register 6.2, the third and fourth to the information inputs of the sixth 6.15 and fifth 6.14 D-flip-flops, respectively, and the fifth the combined clock inputs of the fifth 6.14 and the sixth 6.15 and the information input of the third 6.12 D-flip-flops, the sixth - to the combined clock inputs of the second 6.11, third 6.12 and fourth 6.13 D-flip-flops. The output of the second element 6.4 OR and the output of the shift register 6.2 are respectively the first and second outputs of BORS 6.

The output of the first 6.5 AND element is connected to the first input of the OR-NOT 6.9 element, to the information input of the second 6.11 D-flip-flop, the inverse output of which is connected to the second input of the OR-NOT 6.9 element, the output of which is connected to the installation input in “0” of the binary counter 6.1 and the first 6.10 D-trigger.

The direct outputs of the fifth 6.14 and the sixth 6.15 D-flip-flops through the NAND element are connected to the first input of the third 6.7 D-element, the second input of which is connected to the output of the third 6.12 D-flip-flop, and the output is connected to the first input of the second 6.4 OR element, the second input of which connected to the output of the fourth 6.13 D-trigger. The output of the first 6.3 element OR is connected to the counting input of the binary counter 6.1, the three most significant bits of which are connected in order of decreasing precedence, respectively, to the first and second inputs of the second 6.6 element AND and the clock input of the first 6.10 D-trigger, connected by a direct output to the first inputs of the first 6.3 element OR, the first 6.5 element AND and the installation input to “0” of shift register 6.2, the information input of which is connected to the inverse output of the first 6.10 D-trigger, and the output is to the information input of the fourth 6.13 D-trigger.

The first input of BORS 6 is connected to the output of the multiplexer 2.2 of the reference frequency driver 2 (Fig. 1), the second to the output of element 3.3 of the signal analyzer 3, the third and fourth to the outputs of the last (2 ^m ) and additional (2 ^{m + 1} ) bits, respectively counter 4.1, the fifth - to the output of the D-trigger 4.3 of the shaper clock 4, the sixth - to the output of the master oscillator 1.

The proposed device performs the analysis of incoming signals, auto-clock frequency and decoding information similarly to the prototype device. Automatic coordination of speeds when the reception speed exceeds the transmission rate and when the transmission speed exceeds the reception rate is as follows.

When the power is turned on, the memory elements of the device can be in an arbitrary state, while the first 6.10 D-trigger, if it is in the state “0” by direct output, after the transition period is set to state “1” by the signal from the output of the second 6.6 AND element, allocated during operation of the binary counter 6.1, the counting input of which through the first 6.3 element OR receives pulses of the reference frequency F _op from the output of the multiplexer 2.2. Signal log. “1”, coming from the direct output of the first 6.10 D-flip-flop to the installation input in “0” of shift register 6.2, the BFKS 7 reverse counter at the control input (± 1) is set to the summing mode.

At the output of the node forming the reference frequency 2, the value of the reference frequency can be equal to, and also greater or less than the required value.

When setting the reference receive frequency corresponding to the coordinated work of the transmitting side with the receiving side, at the moment of the leading edge of the next correction pulse from the output of the AND 4.3 element, the combination “10” is set at the direct outputs of the fifth 6.14 and the sixth 6.15 D-flip-flops, as a result of which the element’s output AND NOT 6.8 there is a log. “0”, blocking the passage of the correction pulse through the third 6.7 AND element and the second 6.4 OR element to the counting input of the BFKS 7 counter. Due to this, the state of the BFKS 7 counter does not change, and, therefore, the speed code that determines the nominal frequency is not changed.

At the agreed reception and transmission rates, the last bit of the counter of the time interval 10 is in the “1” state, blocking the arrival of pulses through the OR 9 element to its counting input and keeping the high bits 7.2 of the BFKS 7 counter and RS-trigger 11 in the “zero” state, while the latter, using the And 12 element, blocks the passage of pulses from the second output of the signal analyzer 3 to the control input of the memory block of the speed code 8, thereby ensuring the constancy of the speed value.

If the value of the reference reception frequency is higher than required, then at the moment of the appearance of the next correction pulse from the output of element 4.3 (Fig. 1), the last (2 ^m ) and additional (2 ^{m + 1} ) bits of the binary counter 4.1 are set to “1”. On the leading edge of the correction pulse, the fifth 6.14 and the sixth 6.15 D-flip-flops (Fig. 3) are set to “1” and a log appears at the output of the AND-NOT 6.8 element. “1”, allowing the passage of the correction pulse through the third 6.7 AND element and the second 6.4 OR element to the counting input of the BFKS 7 reverse counter, located, as was mentioned above, at the control input in the summing mode. As a result, the state of the BFKS 7 reversible counter is increased by one, which corresponds to a lower value of the reference frequency.

If the reference reception frequency is lower than required, then the coordination is as follows. Using the binary counter 6.1 and the second 6.6 element And at the output of the first 6.10 D-trigger, a time interval is formed, the value of which, expressed in periods of the reference frequency, is defined as

N = 7 · 2 ^m-3 ,

where m≥3 is the number of bits of the binary counter 6.1.

The formation of the interval (N) starts from the moment the first 6.5 element AND pulse arrives at the input from the output of element 3.3, which appears during each alternating sign (when changing from “1” to “0” or from “0” to “1”) in the input sequence to information input 13 (figure 2) of the device. Using the circuit performed on the second 6.11 D-trigger and the OR-NOT 6.9 element (Fig. 3), a short pulse is generated, setting the binary counter 6.1 and the first 6.10 D-trigger to “0”. As a result of this, shift register 6.2 gets the opportunity to advance “1”, coming from the inverse output of the first 6.10 D-trigger, by alternating pulses from the output of element 3.3. In the case under consideration, when the reference reception frequency is lower than the required, at least two pulses arrive at the clock input of the shift register 6.2 during the interval formation time and “1” appears at the output of the shift register 6.2, which translates the BFKS 7 counter counter via the control input (± 1 ) into the subtraction mode, and after a short delay created by the fourth 6.13 D-flip-flop, it enters through the second 6.4 element OR to the counting input of the BFKS 7 counter, transferring it to the previous state corresponding to a higher value of porn frequency. The process continues until the required speed code appears at the output of the reversible counter, and at the output of the reference frequency driver 2 (Fig. 1) the required value of the reference frequency.

Thus, with each distortion of 2 or more times the duration of the signal of the encoded sequence coming from the communication line to the information input 13 of the device (Fig. 2), a pulse appears at the first output of the BORS 6, at the output of the OR element 6.4 of Fig. 3 from the first output of the unit for determining the mismatch of speeds 6 to the installation input to “0” of the counter of the time interval 10 (Fig. 2), while the signal “0” from the output of the last one unlocks the senior bits 7.2 of the reverse counter BFSK 7, and the counter of the time interval 10 starts counting pulses from the second output of the signal analyzer 3 (from the output of element 3.3, Fig. 1). At the same time, the reversible counter BFKS 7 sums (or subtracts) the pulses arriving at its counting input from the first output of the speed mismatch determination unit 6 (from the output of element 6.4 of FIG. 3). When the quality of the communication channel is not worse than the specified number of distortions in the duration of the signals in the time interval determined by the counter 10 of figure 2, does not cause overflow of the reverse counter and the appearance of “1” in its last digit (at the output of the overflow signal of the reverse counter BFKS 7), because . earlier, the counter of the time interval 10 overflows, the “unit” from the output of the last digit of which its operation is blocked, the senior bits 7.2 of the BFKS 7 reverse counter are set to “0” and the “zero” state at the output of the RS-trigger 11 is confirmed, so the speed code remains unchanged.

Changing the transmission speed is equivalent to a sharp deterioration in the quality of the channel, as a result of which the time interval counter 10 works without overflow, and the BFKS 7 reverse counter gets the opportunity to count to overflow and puts the RS-trigger 11 into state “1” with the signal from the additional output, making it possible to pass pulses from the second output of the signal analyzer 3 through the And 12 element to the control input of the speed code memory block 8, which provides a change in the speed code at the outputs of the D-flip-flops 8.0 ... 8.i and the corresponding its code changes the value of the reference frequency at the output of the driver of the reference 2 frequencies.

Thus, due to the introduction of additional high-order (7.2) bits of the reverse counter and the use of averaging the number of distortions of the signal duration taking into account the sign (in the direction of increasing or decreasing the duration) at a given time interval, the proposed device achieved a new quality, namely, the ability to work on channels with interference, while compared with the prototype significantly reduces the likelihood of a false determination of the mismatch of transmission and reception speeds and the associated loss of information.

The number of bits of the counter of the time interval 10 and the senior bits 7.2 of the reverse counter BFKS 7 is determined based on the probability of distortion of the signal element in the communication line ( _RE ).

So, at Р _Э <0.05 (i.e., with the average number of distortions in the communication line not exceeding 5%), the number of bits of the counter of the time interval 10 is selected from the condition that “1” appears in its last discharge with the worst (in this case - uniform) distribution of distortion:

where n is the number of bits of the counter of the time interval.

When R _E = 0.05, the nearest larger value of n corresponding to expression (1) is 5.

The number of senior bits 7.2 of the reverse counter 7.2 is selected from the condition of preventing overflow on the counter interval of the time interval 10:

where k is the number of high order bits 7.2 of the reverse counter.

When R _E = 0.05, the nearest larger value of k corresponding to expression (2) is 6.

Sources of literature

1. Knyazkin B.C., Presnyakov Yu.V., Troshanov V.A. Decoder. Patent RU No. 2088044, M. Cl. H 03 M 5/22.

2. Goryunov V. A., Kolesnikov A. V., Kotov V. I., Troshanov V. A. Device synchronization and decoding. Utility Model Certificate No. 16809, M. Cl. H 03 M 5/22.

3. Goryunov V. A., Kolesnikov A. V., Kotov V. I., Ovchinkin G. M., Troshanov V. A. Digital information receiver. Utility Model Certificate No. 18331, M. Cl. H 03 M 5/22.

Claims (2)

1. A discrete information receiver with automatic matching of transmission and reception rates, comprising a master oscillator, a reference frequency driver, a signal analyzer, a clock frequency generator, a decoder, an AND element, a time interval counter, an OR element connected to a counting input of a time interval counter, controlling and information inputs, clock and information outputs, while the output of the master oscillator is connected through the driver of the reference frequency to the first inputs of the signal analyzer, a clock generator and a decoder, the output of which is connected to the information output of the device, the information input of which is connected to the second input of the signal analyzer, the first output of which is connected to the second input of the decoder, and the second to the second input of the clock generator, the first output of which is connected to the clock output devices and to the third input of the decoder, the second to the fourth input of the decoder, the fifth input of which is combined with the third input of the frequency driver and connected to the control input of the device characterized in that it includes a speed mismatch determination unit, a speed code generation unit, a speed code memory unit and an RS trigger, while the output of the reference frequency driver and the output of the master oscillator are additionally connected to the first and sixth inputs of the speed mismatch determination unit , the third, fourth and fifth inputs of which are connected respectively to the third, fourth and fifth outputs of the frequency driver, the second input to the second output of the signal analyzer, and the first the second and second outputs, respectively, with the counting and control inputs of the speed code generation unit, executed on a reversible counter, the outputs of which are connected to the information inputs of the speed code memory unit, the outputs of which are connected to the control inputs of the reference frequency driver, and the output of the overflow signal of the reversing counter of the formation unit the speed code is connected to the installation input in “1” of the RS-flip-flop, the output of which is connected to the second input of the AND element, the output of which is connected to the control input of the memory unit This is the speed code, and the first input is combined with the first input of the OR element and connected to the second output of the signal analyzer, the input to the “0” counter of the time interval is connected to the first output of the speed mismatch determination unit, and the output to the second input of the OR element, to the input blocking the high bits of the reversible counter of the speed code generation unit and the setting input to “0” of the RS trigger. 2. The device according to claim 1, characterized in that the unit for determining the mismatch of speeds contains a binary counter, a shift register, the first and second elements of OR, the first, second and third elements of AND, the element AND NOT, the element OR NOT, the first, second , the third, fourth, fifth and sixth D-flip-flops, the first input of the speed mismatch determination unit being connected to the first input of the first OR element, the second to the combined first input of the first AND element and the clock input of the shift register, the third and fourth to information inputs, respectively of the fifth and fifth D-flip-flops, the fifth - to the combined clock inputs of the fifth and sixth and the information input of the third D-flip-flops, the sixth - to the combined clock inputs of the second, third and fourth D-flip-flops, the output of the second OR element and the output of the shift register are respectively the first and the second outputs of the speed mismatch determination unit, the output of the first AND element is connected to the first input of the OR-NOT element and to the information input of the second D-trigger, whose inverse output is connected to the second input of the OR-NOT element for which it is connected to the installation inputs at “0” of the binary counter and the first D-flip-flop, the direct output of the fifth and the inverse output of the sixth D-flip-flops through the OR-NOT element are connected to the first input of the third AND element, the second input of which is connected to the output of the third D- trigger, and the output is with the first input of the second OR element, the second input of which is connected to the output of the fourth D-trigger, the output of the first OR element is connected to the counting input of the binary counter, the three high-order bits of which are connected in order of decreasing seniority, respectively but to the first and second inputs of the second AND element and the clock input of the first D-trigger, the information input connected to the output of the second AND element, direct output - with the second inputs of the first OR element, the first AND element and the input to the shift register “0”, information whose input is connected to the inverse output of the first D-trigger, and the output to the information input of the fourth D-trigger.

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