JPH0786926A - Dpll circuit - Google Patents

Abstract

PURPOSE:To make the high-speed synchronization characteristic compatible with the low-sensitivity degradation amount and further to keep the stability of a phase control operation after phase lock. CONSTITUTION:A count signal outputted from an up-down counter 13 to be used as a phase comparator/control circuit so as to control a selector circuit 11 is shifted for the unit of a bit by using a timer 16 and a shift circuit 15. Thus, the phase controlled variable is enlarged until phase lock and after the phase lock, the phase controlled variable is reduced rather than that before the phase lock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a DPLL for discriminating received burst data signals arriving from a plurality of transmission circuits.
Regarding the circuit.

[0002]

2. Description of the Related Art An optical communication system using an optical fiber having excellent characteristics such as low loss and wide bandwidth has been introduced mainly in a backbone system of a public communication network and has a long distance of 2.4 Gbit / sec. A large capacity system (2.4 Gb / s new synchronous optical transmission system) has already been put to practical use.

Furthermore, in recent years, in order to provide broadband communication services against the background of the development of such optical transmission technology,
Research and development are being carried out on optical subscriber transmission systems. In such an optical subscriber transmission system, in order to make the optical communication system economical, for example, as shown in FIG. 3, one master station 30 and a plurality of slave stations 32, 33, 34 are provided in the optical star coupler 31. A passive double star (PDS) configuration in which optical fibers 35, 36, 37, and 38 are connected via an optical fiber is under study.

In this configuration, data signals from the transmitters of a plurality of slave stations arrive at the master station in bursts without bit synchronization. For this reason, in the actual burst data signal sequence, a preamble signal for bit synchronization is generally added before the data signal. However, since the increase in the number of bits of this preamble signal reduces the transmission efficiency of the data signal, it is possible to synchronize with a circuit that performs timing extraction from such a received burst data signal with a preamble signal with a small number of bits. "High-speed synchronization characteristics" are required. Further, in the PDS configuration of FIG. 3, all slave stations do not always communicate in the assigned time slot, so that a zero code continuation with a long number of bits may occur in the master station. Therefore, the timing extraction circuit is also required to have "withstanding characteristics against a long number of consecutive zero codes".

Here, in a timing circuit applied to a long distance transmission system, a tank circuit such as a SAW filter is often used. In this circuit, "high-speed synchronization characteristic",
It is difficult to satisfy both the required characteristics because there is a trade-off relationship between the two required characteristics, that is, "proof strength against long-bit zero code continuation". For this reason, in an optical subscriber transmission system such as a PDS configuration, a DPLL circuit including digital elements such as a counter and a selector is being studied in order to satisfy two required characteristics.

FIG. 2 shows a conventional example of the DPLL circuit described in Japanese Patent Application No. 05-128555. Conventional D in FIG.
In the PLL circuit, the received burst data signals that have arrived from the transmission circuits of a plurality of slave stations are delayed by using the shift register 20 that operates by a high-speed clock signal, and are converted into multi-phase burst data signals. Then, the multiphase burst data signals output from the shift register 20 are input to the selector circuit 21. Also, DPL
The clock signal input to the L circuit is input to the up / down counter 23 and the data identification circuit 24, and is also output from the DPLL circuit as a clock signal.

On the other hand, the up / down counter 23 receives a burst data signal of one phase selected by the selector circuit 21 at its clock terminal and a clock signal at its up / down control terminal. In the up / down counter 23 to which such a signal is input, the counter is incremented by +1 or decremented by -1 depending on the state ("H" or "L") of the clock signal at the change point of the burst data signal, and the count thereof is performed. The value is input to the selector circuit 21.

Therefore, if the selector circuit 21 is controlled by using the count signal from the up / down counter 23 so that the change point of the clock signal in the up / down counter 23 and the change point of the burst data signal coincide with each other, a plurality of sub-circuits are generated. Even if the received data signal from the transmitter of the station arrives in a burst state without bit synchronization, the phase relationship between the burst data signal and the clock signal input to the data identification circuit 24 is Is almost constant. As a result, it becomes possible to output from the DPLL circuit an identification burst data signal for which data identification is always performed in the data identification circuit 24 in the optimum phase relationship.

[0009]

In the conventional DPLL circuit, the count value of the up / down counter 23 is 1.
The amount of phase control due to two changes was fixed. In such a DPLL circuit, if the phase control amount is increased and synchronization is established with a small number of up / down counts in order to satisfy the high-speed synchronization characteristic, the amount of phase variation after synchronization is large, so that data identification is performed. The discrimination phase margin in the circuit 24 decreases and the sensitivity deterioration amount increases. On the other hand, if the phase control amount is reduced to reduce the sensitivity deterioration amount, the number of up / down counts for establishing the synchronization increases, so that the synchronization characteristic deteriorates. That is, the conventional DPL
In the L circuit, there is a problem that there is a trade-off relationship between the high-speed synchronization characteristic and the low sensitivity deterioration amount.

When noise or the like is mixed after the phase synchronization is performed, the up / down counter 2 due to noise is used.
Since the fluctuation of the count value of 3 directly affects the selector circuit 21, there is a problem that the phase control operation becomes unstable.

An object of the present invention is to solve such a conventional problem, to achieve both high-speed synchronization characteristics and low sensitivity deterioration amount, and further to maintain stability of phase control operation after phase synchronization.

[0012]

In order to solve the above-mentioned problems, the means provided by the present invention is a DPLL circuit for identifying a received burst data signal, wherein the received burst data signal is detected by using a high speed clock signal. Delay,
A shift register for generating a multi-phase burst data signal, a selector circuit for selecting a burst data signal of one phase from the multi-phase burst data signal generated in the shift register, and the selector circuit selected by the selector circuit. A data identification circuit for identifying a burst data signal of one phase using a clock signal, and a timer for measuring a predetermined time after a burst reset signal input in synchronization with the received burst data signal and outputting a timer signal. For comparing the phase relationship between the burst data signal of one phase output from the selector circuit and the clock signal, and synchronizing the burst data signal of one phase output from the selector circuit with the clock signal. A phase comparison / control circuit that outputs a control signal and the timer signal Phase control signal from the comparator and control circuit is shifted bit by bit, characterized in that it is composed of a shift circuit for outputting to said selector circuit.

[0013]

In the present invention, the count signal output from the up / down counter used as the phase comparison / control circuit and controlling the selector circuit is shifted bit by bit using the timer and shift circuit. As a result, a large amount of phase control is achieved until synchronization and a smaller amount of phase control is achieved after synchronization, which makes it possible to achieve both high-speed synchronization characteristics and low sensitivity deterioration amount.

It is also possible to eliminate the instability of the phase control operation after phase synchronization when noise or the like is mixed.

[0015]

FIG. 1 shows an embodiment of the present invention. The operation of the DPLL circuit of the present invention will be described with reference to FIG.

In the DPLL circuit of FIG. 1, the received burst data signals arriving from the transmission circuits of a plurality of slave stations are delayed by using the shift register 10 operated by the high speed clock signal and converted into a multi-phase burst data signal. To be done. Then, the multiphase burst data signal output from the shift register 10 is input to the selector circuit 11. Further, the clock signal input to the DPLL circuit is input to the up / down counter 13 and the data identification circuit 14, and is also output as a clock signal from the DPLL circuit.

On the other hand, in the up / down counter 13, the burst data signal of one phase selected by the selector circuit 11 is input to the clock terminal, and the clock signal is input to the up / down control terminal. In the up / down counter 13 to which such a signal is input, the counter is incremented by +1 or decremented by -1 depending on the state ("H" or "L") of the clock signal at the change point of the burst data signal, and the count is counted. The value is input to the shift circuit 15.

Here, the shift circuit 15 operates differently before and after phase synchronization. This operation is shown in FIG.
Will be explained.

Before the phase synchronization, the control signal from the up / down counter 13 is shifted bit by bit to the upper bit so that "L" is output from the least significant bit. As a result, when the count value of the up / down counter 13 changes by ± 1, the output of the shift circuit 15 changes by ± 2. Therefore, the selector circuit 11 selects the multi-phase data signal from the shift register 10 every other phase, so that the phase control amount is equivalently doubled. After the phase synchronization, as shown in (1) after the phase synchronization in FIG. 4, the control signal from the up / down counter 13 is shifted from the state before the phase synchronization to the lower bits bit by bit. This allows
The count value of the up / down counter 13 becomes the output value of the shift circuit 15 as it is, and the selector circuit 11 sequentially selects the multi-phase data signals phase by phase. As described above, a data signal having a large amount of phase control can be used until synchronization, and a data signal having a smaller amount of phase control than that before synchronization can be used after synchronization.

The switching in the shift circuit 15 is performed as follows, for example. First, the timer 16 is reset by a burst reset signal input in synchronization with the received burst data signal, and then the received burst data signal is received up to the number of preamble bits required for synchronization using the data signal having a large phase control amount. Count the number of bits. Then, when the set count number is reached, a control signal (“H” signal in FIG. 4) is output from the timer 16, and the shift circuit 15 is switched using the control signal to decrease the phase control amount. In addition,
In order to prevent a change in the polyphase data signal selected by the selector circuit 11 when the phase control amount is switched by the shift circuit 15, the control signal output from the timer 16 is also applied to the preset terminal of the up / down counter 13. The input data signal is selected so that the data signal selected before switching the shift circuit 15 is selected immediately after switching. Here, the signal input to the CLK terminal of the timer 16 may be the burst data signal output from the selector circuit 11, as long as it is synchronized with the received burst data signal.

From the above, the selector circuit 11 is passed through the shift circuit 15 using the count signal from the up / down counter 13 so that the change point of the clock signal in the up / down counter 13 and the change point of the burst data signal coincide with each other. The DPL of this configuration is controlled by controlling
In the L circuit, the received data signals from the transmitters of plural slave stations are
Even if the data arrives in bursts without bit synchronization, the phase relationship between the burst data signal and the clock signal input to the data identification circuit 14 becomes substantially constant after phase synchronization. Therefore, the data identification circuit 14
In the above, it is possible to output from the DPLL circuit an identification burst data signal in which data identification is always performed in the optimum phase relationship.

That is, in the present invention, in order to solve the above-mentioned problems, the count signal output from the up / down counter 13 for controlling the selector circuit 11 is shifted in bit units using the timer 16 and the shift circuit 15. Therefore, the amount of phase control is large until synchronization, and the amount of phase control after synchronization is smaller than that before synchronization, and it is possible to achieve both high-speed synchronization characteristics and low sensitivity deterioration amount.

Further, when noise or the like is mixed in after phase synchronization, fluctuations in the count value of the up / down counter 13 due to the noise directly affect the selector circuit 11, and the phase control operation may become unstable. But,
In this case, as an example of the shift operation after the phase synchronization of the shift circuit 15, as shown in the after phase synchronization (2) of FIG.
The bits are shifted bit by bit so that "L" is output from the most significant bit. As a result, the count value of the up / down counter 13 is halved on the selector circuit 11 side.
It becomes possible to reduce to the count value of. Therefore,
The fluctuation amount of the count value in the up / down counter 13 can be compressed by using the shift circuit 15, and the instability of the phase control operation when noise or the like is mixed can be removed.

Instead of the up / down counter 13, a circuit whose holding value changes depending on whether the state of the clock signal is "H" or "L" at the changing point of the data signal from the selector circuit 11, For example, the same effect can be obtained by using a shift register or the like.

Further, since the timer 16 only needs to output the control signal a predetermined time after the burst reset signal is input, not only the structure for counting the received burst data signal but also a mono-multi circuit or the like may be used. .

[0026]

As described above, according to the present invention, the count signal output from the up / down counter used as the phase comparison / control circuit for controlling the selector circuit is
Since a timer and shift circuit are used to shift in bit units, a large amount of phase control is achieved until synchronization and a smaller amount of phase control is achieved after synchronization, making it possible to achieve both high-speed synchronization characteristics and low sensitivity degradation. It will be possible.

Further, by changing the shift amount in the shift circuit after the phase synchronization, it is possible to eliminate the instability of the phase control operation when the noise or the like is mixed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a PLL circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of a conventional DPLL circuit.

FIG. 3 is a diagram showing an example of a passive double star configuration.

FIG. 4 is a diagram showing an example of operation of a shift circuit.

[Explanation of symbols]

 10, 20 shift register, 11, 21 selector circuit, 13, 23 up / down counter, 14, 24 data identification circuit, 15 shift circuit, 16 timer, 17, 25 DPLL circuit, 30 master station, 31 optical star coupler, 32, 33,34 slave station, 35,36,37,38 optical fiber.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04B 10/14 10/04 10/06 H04L 12/44 8732-5K H04L 11/00 340

Claims (1)

[Claims] 1. A DPLL circuit for identifying a received burst data signal, the shift register delaying the received burst data signal using a high speed clock signal to generate a multi-phase burst data signal, and the shift register generated in the shift register. Selector circuit for selecting a burst data signal of one phase from the selected multi-phase burst data signal, and a data identification circuit for identifying the burst data signal of one phase selected by the selector circuit using a clock signal A timer for measuring a predetermined time after a burst reset signal input in synchronization with the received burst data signal and outputting a timer signal, a burst data signal of one phase output from the selector circuit, and the clock The phase relationship of signals is compared, and the signals output from the selector circuit are output. A phase comparison / control circuit that outputs a control signal for synchronizing a burst data signal of one phase with the clock signal; and a control signal from the phase comparison / control circuit that is shifted in bit units by the timer signal. DP comprising a shift circuit for outputting to the selector circuit
LL circuit.