KR0141301B1 - Circuit for generating the data clock signal capable of phasing - Google Patents

Abstract

This phase-adjustable data clock signal generation circuit finely adjusts the phase of the data clock signal, which is twice as fast, in order to generate the data clock signal provided from the IOM2 bus into a signal suitable for the voice coding method performed by the wireless base station and the handset. This is to enable the generation of a high speed data clock signal. To this end, the circuit comprises a first clear signal generator, a first counter, a DCL detector, a first buffer, a flip-flop, a phase adjuster, a second counter, and a first comparator, which is used to make a voice at a wireless base station and a handset. A data clock signal adaptive to a coding scheme can be provided.

Description

Phase-adjustable data clock signal generation circuit

1 is a data clock signal generation circuit diagram capable of phase adjustment according to the present invention;

FIG. 2 is a timing diagram of a part of the circuit diagram shown in FIG.

* Explanation of symbols for main parts of the drawings

100: IOM2 bus unit 110: first high speed clear signal generator

120: oscillator 130: second high speed clear signal generation unit

140: third high speed clear signal generation unit 150: counting means

160: buffer 170: DCL detection unit

180: fifth counter 190: comparator

200: flip-flop 210: phase adjustment unit

The present invention relates to a connection device between a DECT (Digital European Codeless Telecommunication) wireless base station and an ISDN switch, and in particular, an ISDN oriented connection of a comprehensive information communication network in a DET wireless base station. Modulo 10M2) Phase-adjustable data clock signal generated by the operator to arbitrarily adjust the data clock signal (DATA ClOCK: DCL) used in the bus to have a period suitable for use in radio base stations and handsets. It relates to a generation circuit.

Dect-based radio base stations are fixed stations that employ a personal mobile communication system as defined by the European Telecommunications Standards Committee, and use the IOM2 bus for communication between ISDN exchanges and handsets (or terminals). The IOM2 bus is composed of frame sync signal (PSC), data clock signal (DCL), uplink data (DUP) and downlink data (DDP). The clock signal is generated, and DCL is allowed to generate 192 clock signals in one frame, and two data clocks are used for one data transmission of uplink data and downlink data. Up and down can be received.

These IOM2 buses are designed based on ISDN exchanges, so that 64K bits per second are transmitted when processing voice information (since ISDN exchanges process voice signals using pulse code modulation (PCM)), generating data clock signals. Doing. However, between the radio base station and the handset, and inside the handset, the adaptive pulse code modulation (ADPCM) method is used to process 32K bits per second voice signal, which doubles the voice signal compared to the ISDN switch. It is difficult to use the data clock signal provided from the bus as it is for the radio base station and the handset.

In order to improve this problem, a circuit for generating a data clock signal having a cycle twice as fast has been proposed, but it is also fixed, which is not suitable for a wireless base station or a handset having a higher voice compression rate.

Accordingly, an object of the present invention is to provide a high speed data clock by fine-tuning the phase of the data clock signal, which is twice as fast, in order to generate a data clock signal provided on the IOM2 bus into a signal suitable for a voice coding method performed at a wireless base station and a handset. The present invention provides a data clock signal generation circuit capable of adjusting phase to enable generation of a signal.

In order to achieve the above object, the circuit according to the present invention is a modular IMO2 connection system for generating a frame synchronization signal (FSC) and a data clock signal (DLC) for data transmission and reception with a general information communication network switch or terminal. A circuit for generating a data clock signal suitable for a voice coding scheme made in a radio base station having a bus unit and an oscillator for generating a high frequency clock signal; A first clear signal generation section for generating a clear signal in synchronization with the frame synchronization signal and the high frequency clock signal output from the oscillator, and a first clear signal generation section for clearing the clock signal output from the oscillator 1 counter; A detection unit for clearing by a signal output from the first clear signal generation unit and counting a data clock signal to detect the maximum number of processing bits per second processed by the voice coding method of the radio base station; A first buffer for temporarily storing a value corresponding to a quarter period of the data clock signal applied from the first counter in synchronization with the output signal of the detector; A flip-flop for generating a data clock signal adjusted to be suitable for a voice coding method; a flip by comparing a count value of a high frequency clock signal cleared at the edge of the data clock signal and output from the oscillator to a phase adjustment reference value arbitrarily set by an operator A phase adjuster for adjusting the phase of the adjusted data clock signal output from the flop; A second counter for counting a high frequency clock signal output from the oscillator by controlling the clear state by the signal output from the phase adjuster; And a first comparator for controlling a preset state of the flip-flop by detecting a point having the same value by comparing the output signal of the first buffer with the output value of the second counter.

Next, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates an embodiment of a data clock signal generation circuit according to the present invention, and includes a frame synchronization signal FSC and an oscillator output from an IOM2 bus unit 100, an oscillator 120, and an IOM2 bus unit 100. The first high speed clear signal generating unit 110 and the data clock signal DCL output from the IOM2 bus unit 100 and the oscillator 120 to generate a clear signal in synchronization with the high frequency clock signal output from the 120. A second high speed clear signal generator 130 for generating a clear signal in synchronization with the high frequency clock signal to be cleared, in synchronization with a high frequency clock signal output from the oscillator 120 and an antiphase signal (/ DCL) of the data clock signal The data is generated by signals output from the third high speed clear signal generation unit 130, the second high speed clear signal generation unit 130, and the third high speed clear signal generation unit 140 for generating a signal. The oscillator 120 is cleared by the signal output from the edge detector G4 and the first fast clear signal generator 110 for detecting the falling edge of the clock signal DCL or the reverse data clock signal / DCL. The counting means 150 for counting the signal output from the controller, the DCL detector 170 for detecting the 32nd DCL signal by counting the DCL signal output from the IOM2 bus unit IO0, and synchronized with the DCL detector 170. A buffer 160 for temporarily storing the number of high frequency clock signals corresponding to a quarter cycle of the DCL cycle among the values counted by the counting means 150. For adjusting the phase of a double DCL signal to be generated using a phase adjustment reference value set by a CPU (not shown) and a value obtained by counting a high frequency clock signal cleared by the edge detector G4 and output from the oscillator 120. A fifth counter 180 and a signal output from the buffer 160 and the fifth counter 180 for counting the high frequency clock signal provided by the oscillator 120 and cleared by the signal output from the phase adjuster 210 and the phase adjuster 210. 5 Comparator 190 for comparing the signals output from the counter 180, preset by the signal output from the comparator 190 (/ PR) and reset by the signal output from the phase adjuster 210 (/ RESET) and the flip-flop 200 for outputting the adjusted DCL signal.

2 is an operation timing diagram of a portion shown in FIG.

Next, an embodiment according to the present invention will be described in detail with reference to FIGS. 1 and 2.

First, the IOM2 bus unit 100 includes an IOM2 bus master controller 101 and a slave controller 102, and separates the data received from an exchanger (not shown) into a D channel and a B channel, respectively. The downlink signal processing may be performed to another device in the wireless base station, or the data from another device of the terminal or wireless base station not shown may be signaled upstream to an exchanger not shown. Such an IOM2 bus unit (IO0) is described above. As described above, it is composed of a frame synchronization signal (hereinafter referred to as FSC), a data clock signal (hereinafter referred to as DLC), an uplink transmission data (DUP), and a downlink transmission data (DDP) transmission line.

The first fast-clear signal generating unit 110 is composed of three D-flop flops 111, 112, and 113, two buffers B1 and 82, and a logical multiplication device G2. Synchronized with the FSC signal output from the unit 100 and the high frequency clock signal output from the oscillator 120, which will be described later, is generated as a clear signal of the count means 150 and the DCL detector 170, which will be described later. That is, the FSC signal generated when the data transfer of the IOM2 bus unit 100 starts is performed by the clock of the D flip-flop 111 having the highest potential Vcc connected to the input terminal D and the preset terminal / PR. It is applied to the terminal CLK. As described above, the D flip-flop 111 outputs a high logic level signal through the output terminal Q at the rising edge of the FSC signal generated at the 125usec cycle and a low logic level to the inverted output terminal / Q. Output the signal. The signal output through the output terminal Q of the D flip flop 111 is transmitted to the input terminal D of the D flip flop 112 connected to the next stage. The D flip-flop 112 transmits the high logic level applied to the D input terminal to the input terminal D of the next D flip flop 113 in synchronization with the rising edge of the clock signal output from the oscillator 120. . The D flip-flop 113 also outputs a high logic state signal in response to a signal applied to the input terminal D in synchronization with the clock signal output from the oscillator 120, but inverts the D flip-flop 113 having a low logic state. Only the output signal / Q is transmitted to the buffer 81. The low logic state signal transmitted to the buffer 81 is applied to one input terminal of the logical multiplication device G1 through the buffer 82. The AND device G1 performs an AND operation on the reset (/ RESET) signal and the output signal of the buffer 82 to reset the D flip-flops 111, 112, and 113 simultaneously. The two D flip flops 112 and 113 and the buffers 31 and 82 used here are cleared of the counting means 150 and the DCL detector 170 as described above in which the D flip flop 111 is synchronized with the FSC signal. After outputting the signal, the time to be reset is delayed by a predetermined time. The inverted output signal (/ Q) of the D flip-flop 111 is provided as a clear signal of the count means 150 and the DCL detector 170, which will be described later.

The oscillator 120 generates a high frequency clock signal and is configured in the same manner as in the prior art.

The counting means 150 includes a first counter 151 and a second counter 152, and counts the high frequency clock signal OSC provided by the oscillator 120 as shown in FIG. 1 The clear state is controlled by the signal output from the high speed clear signal generator 110.

That is, the first and second counters 151 and 152 are configured as 8-bit counters, and the first and second counters 151 and 152 are configured as clock signals of the first counter 151 by using the most significant output bit Q7 of the second counter 152 from the oscillator 120. By counting the applied clock signal, it can be replaced by one 16-bit counter. The counted value is cleared by the clear signal provided by the first high speed clear signal generator 110, and the counted value is transmitted to the buffer 160.

The DCL detector 170 includes an 8-bit third counter 171, a plurality of inverters IN2 to 8, and a logical multiplication device G5 to generate a DCL generated from the IOM2 bus unit 100 for the 32nd time. To detect. In this case, the 32nd DCL is detected because the voice coding scheme used in the wireless base station and the handset is configured to transmit data of 32K bits per second, and the voice coding scheme performed in the wireless base station and the handset is an example. The number of DCLs to be detected when processing bits per second may be set differently.

The third counter 171 of the DCL detector 170 counts the DCL output from the IOM2 bus unit 100 while the clear state is controlled by the signal output from the first high speed clear signal generator 110. . The counted result is transmitted to the inverters IN2 to 8 and the logical multiplication device G5 connected to the next stage. The inverters IN2 to 8 and the logical product G5 output a high logic signal to the clock terminal CLK of the buffer 160 to be described later when the count value output from the third counter 171 becomes 32. It is made up of logical structure.

The buffer 160 has a Dl-D7 input terminal of the input terminals D0-D7 connected to the Q0 to 6 output terminals of the first counter 151 in the counting means 150, and the D0 input terminal is connected to the second counter 152. 8-bit D flip-flop connected to the Q7 output terminal and reset by a reset signal (/ RESET) provided from a central processing unit (CPU) (not shown). The count value provided by the means 150 is temporarily stored and then transmitted to one input terminal A of the comparator 190 to be described later. At this time, the count value provided by the counting means 150 is the number of high frequency clock signals corresponding to a quarter period of the DCL applied as shown in the second diagram (b).

Meanwhile, the second fast clear signal generator 130 has the same structure as the first fast clear signal generator 110 and generates the fast clear signal for the DCL signal output from the IOM2 bus unit 100. It is to.

That is, in order to generate the clear signal, the second high speed clear signal generator 130 provides the clock terminal CLK of the D flip-flop 131 when the DCL signal is output from the IOM2 bus unit 100. The D flip-flop 131 outputs a high logic level equal to the second (c) degree at the rising edge of the DCL signal applied through the clock terminal at the same period as the second (b) degree, and is returned by the logical multiplication device G3. Is set. The logical multiplication device G3 generates a D flip-flop 131 in synchronization with a reset signal / RESET provided from a CPU (not shown) and a high frequency clock signal generated by the second oscillator 120 in the oscillator 120. The output signal Q is logically multiplied by the signal applied via the two D flip-flops 132 and 133 and the buffers B3 and B4. The number of D flip-flops used here may be adjusted according to the processing time, and the high speed clear signal output from the D flip-flop 131 is transmitted to the edge detector G4, which will be described later.

The third high speed clear signal generation unit 140 is configured by adding the inverter IN1 to the same structure as the first and second high speed clear signal generation units 110 and 130 described above, and thus, the second high speed clear signal generation unit 130. This is for generating a clear signal having a reverse phase with the clear signal generated in the < RTI ID = 0.0 > That is, when the DCL clock signal as shown in FIG. 2 (b) is applied from the IOM2 bus unit 100, the clock terminal CLK of the D flip-flop 141 is inverted through the inverter IN1 as shown in the second diagram d. To send). The D flip-flop 141 outputs the signal converted to the high logic level as shown in the second (e) through the output terminal Q at the rising edge of the clock signal inverted as shown in the second (d). The output signal is a logical multiplication device via the D flip-flops 142 and 143 and the buffers 85 and 36 provided at the next stage as in the first and second high speed clear signal generating units 110 and 130 described above. In G3, the D flip-flops 141, 142, and 143 in the third high speed clear signal generation unit 140 are reset by being multiplied by the reset signal / RESET provided from the CPU (not shown). / RES). The high speed clear signal output from the inverted output terminal / Q of the D flip-flop 141 is transmitted to the edge detector G4.

The edge detector G4 is configured as a logic sum element to generate the third high speed clear signal such as the inverted output signal / Q and the second high speed clear signal generator 130 of the second (c) degree and the second (e) degree. The inverted output signal / Q of the unit 140 is ORed and output as shown in FIG. 2 (f). The output signal is transmitted to the phase adjuster 210.

The phase adjusting unit 210 includes a fourth counter 211 which is an 8-bit counter, a D flip-flop buffer 212 which uses a reference value for phase adjustment applied from a CPU (not shown) via a data bus as an input signal. 2 comparator 213 to adjust the phase of the adjusted DCL signal to be output from the flip-flop 200 to be described later.

That is, when the desired phase adjustment value is applied by the operator, the CPU (not shown) analyzes the data and provides the data to the input terminal of the buffer 212. The clock state and the reset state of the buffer 212 are also determined by the CPU described above. Controlled. The buffer 212 transmits an 8-bit type input value applied from the CPU to one input terminal B of the second comparator 213 in synchronization with a clock signal applied from the CPU, and provides a reset signal (provided by the CPU). / RESEl) to clear it.

The fourth counter 211 is cleared by the output signal of the edge detector G4 and counts the clock signal provided from the oscillator 120, and the 8-bit count result value is input to one input terminal A of the second comparator 213. to provide.

The second comparator 213 compares the value counted by the fourth counter 211 with an arbitrary set value applied by the buffer 212 and outputs an active high-non-level signal when the same. The output signal is provided as the clear signal / CLS of the fifth counter 180 and the reset signal / RES of the flip-flop 200.

If the clear state is controlled by the signal output from the phase adjuster 210, the fifth counter 180 counts the clock signal output from the oscillator 120, and the counted value is 8-bit data. Will output The output 8-bit data is transmitted to one input terminal B of the first comparator 190.

The first comparator 190 compares the 8-bit data value applied from the buffer 160 with the data value output from the fifth counter 180 and outputs a high logic level signal when they match each other. The output signal is transmitted to the preset terminal / PR of the flip-flop 200.

The flip-flop 200 is composed of a D-type flip-flop having the highest potential Vcc connected to the input terminal D and the clock terminal CLK, and reset by the signal output from the phase adjuster 210. A DCL signal of which the phase is adjusted by presetting by the signal output from 190) is output.

As shown in FIGS. 2 (g), (h), (i), and (j), the DCL signal finally output from the flip-flop 200 is adjusted in phase by the signal output from the phase adjuster 210. Outputs twice the DCL clock signal. Here, the second (g) is the case where 1 is set at the input terminal of the buffer 212 in the phase adjusting unit 210, the second (h) or 2 is set, and the second (i) is 3 is set. 2 (i) is a case where 3 is set, and 2 (j) is a case where 4 is set, the timing diagram at the upper end is a signal output from the second comparator 213, and the timing diagram at the lower end. Is a signal output from the flip-flop 200.

As described above, the present invention arbitrarily adjusts the phase when the data clock signal (DCL) used in the IOM2 bus is generated at twice the speed, thereby generating a data clock signal adaptive to the voice coding method used in the wireless base station and the terminal. There is an effect that can be provided.

Claims (5)

Comprehensive information network connection type modular (IOM2) bus unit for generating frame synchronization signal (FSC) and data clock signal (DLC) for transmitting / receiving data to / from a general information communication network switch or terminal and an oscillator for generating a high frequency clock signal. A circuit for generating a data clock signal suitable for a voice coding scheme performed at a wireless base station; A first clear signal generator configured to generate a clear signal in synchronization with the frame synchronization signal and the high frequency clock signal output from the oscillator; A first counter that is cleared by the first clear signal generator and counts a clock signal output from the oscillator; A detection unit cleared by a signal output from the first clear signal generation unit, and counting the data clock signal to detect a maximum number of processing bits per second processed by the voice coding scheme of a radio base station; A first buffer for temporarily storing a value corresponding to a quarter period of the data clock signal applied from the first counter in synchronization with an output signal of the detector; A flip-flop for generating a data clock signal adapted to the voice coding scheme; To adjust the phase of the adjusted data clock signal output from the flip-flop by comparing the counted value of the high frequency clock signal cleared at the edge of the data clock signal with a phase adjustment reference value arbitrarily set by an operator and output from the oscillator. Phase adjuster for; A second counter for counting the high frequency clock signal output from the oscillator by controlling a clear state by the signal output from the phase adjuster; And a first comparator for controlling a preset state of the flip-flop by detecting a point having the same value by comparing the output signal of the first buffer and the output value of the second counter. Data clock signal generation circuit. 2. The apparatus of claim 1, wherein the data clock signal generation circuit comprises: a second clear signal generator configured to generate a clear signal in synchronization with the data clock signal output from the IOM2 bus unit and the high frequency clock signal output from the oscillator; A third clear signal generator configured to generate a clear signal in synchronization with an antiphase signal of the data clock signal and the high frequency clock signal; And an edge detector for detecting the edge by ORing the signals output from the first clear signal generator and the second clear signal generator. 3. The apparatus of claim 2, wherein the phase adjuster comprises: a third counter for counting a high frequency clock signal provided from the oscillator by controlling a clear state by a signal output from the edge detector; A second buffer for storing and outputting a phase adjustment reference value set by the operator for a predetermined period of time; And a second comparator for comparing the count value output from the third counter and the phase adjustment reference value transmitted from the second buffer to detect a matching point and providing the second counter and the flip-flop. A data clock signal generation circuit whose phase can be adjusted. 3. The data clock signal generation circuit of claim 1 or 2, wherein the maximum number of processed bits per second in the detector corresponds to 32 bits. 3. The data clock signal generation circuit of claim 1 or 2, wherein the flip-flop is a D-type flip-flop fixedly connected to a data input terminal and a clock signal input terminal.