KR880000552B1 - Data Transmission Circuit of Mobile Cordless Car Telephone - Google Patents

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Description

Data Transmission Circuit of Mobile Cordless Car Telephone

1 is a block diagram of transmission data of a mobile wireless vehicle telephone.

2 is a block diagram of a transmitting unit of a mobile radio telephone of the present invention.

3 is a concrete circuit diagram of FIG.

4 is a timing diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

1: Latch Circuit 2: Shift Register

3: transmission clock synchronous circuit 4: manchester encoder order

5: interrupt signal generator 6: parallel load signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital data communication transmitter of a mobile radio telephone, and more particularly, to a transmission broadband data output control circuit of a manchester encoder for digital data communication of a mobile radio telephone.

Currently, cellular wireless communication is used as a mobile wireless communication system. Cellular wireless communication method divides a certain area into a plurality of communication areas called cells, uses different frequencies for each communication area, and reuses frequency bands used in other areas without interference between areas. It is to increase the call volume, increase the call volume and increase the call quality. In the US, Cellular wireless telephony is being operated by AMPS (Advanced Mobile Phone Service) system developed by Bell Labs and American Radio Teliphone Service (ARTS) system developed by AT & T. In 1984, Korea has begun AMPS-type wireless service service for vehicles.

The AMPS system consists of a central control station (MTSO), a cell site and a mobile cordless car phone. Wired communication is performed between the central control station and the cell site, and wireless communication is performed between the cell site and the mobile radio telephone. The MTSO manages and controls the interconnection between the general telephone network and the AMPS system and the channels assigned to the cell sites. It is a function to prevent disadvantages ("Hand off"). CellSight changes the signal to handle the central control station and the wired network, always monitors the signal strength of the mobile cordless phone in its cell area, provides information to the central control station, and sends the information received from the central control station to the mobile cordless phone. Deliver it. Thus, a telephone call between a general subscriber connected to a central control station and a mobile wireless telephone can be made.

In the AMPS system, the transmit frequency band sent from the mobile cordless phone to the cell site has a bandwidth of 20MHZ of 825-845MHZ and the receive band received from the cell site has a bandwidth of 20MHZ of 870-890MHZ. In addition, each transmit / receive frequency band has 666 channels with a frequency interval of 30KHZ, and performs full duplex communication. In each frequency band, the upper and lower channels are used as control channels (642 channels in total) around the frequency channels 333 and 334 channels, and the remaining 312 upper and lower channels are used as voice channels (624 channels in total). In addition, the data format of the voice channel and the format of the control channel (referred to as a reverse direction) and the voice channel of the cell site transmission (referred to as a reverse direction) in the mobile wireless mobile phone defined and used in the AMPS system are shown in FIGS. It is as showing in FIG. 1 (b).

One frame of the data format of the control channel shown in FIG. 1 (a) includes a 30-bit dotting sequence used for bit synchronization and an 11-bit word sync used for data synchronization; It contains 7-bit cell site ID data indicating a unique number of the cell site. Next to the cell site address data, A system control data A1-A5 and B system control data B1-B5 used in the control channels of the upper and lower 21 channels are loaded. The control data are each 48 bits as shown.

Therefore, the control data is repeated five times the control data used for the registration, identification, and confirmation used in the control channel when the mobile cell phone and the predetermined cell site and the access (Access).

On the other hand, the data format of the voice channel shown in FIG. 1 (b) is a first frame consisting of a 101-bit dosing sequence, an 11-bit word sink, and a 48-bit data A1, a 37-bit dotting sequence, and an 11-bit word sink. And a second frame composed of 48 bits of data A2 and third to fifth frames having the same data format as the second frame are successively connected after the second frame. The data format of the voice channel is used after the access in the above-described voice channel, and the data of the voice channel is data repeated five times used to monitor and instruct the operation status of the mobile wireless mobile phone such as cell site change. Also, according to the AMPS regulations, the dotting sequence is set to 10101010 ... and the word sync is set to 11100010010. Such a data format is disclosed in IEEE Transaction on vehicular Technology, Vol 29, No. 2 pages 238 to 244 published in 1980.

On the other hand, a system of a mobile cordless telephone for use in an AMPS system has been disclosed in pages 123 to 143 of The Bell System Technical Journal, Vol 58, No. 1, published by Bell Labs in January 1979. However, it should be noted that the present invention is not related to all of the systems disclosed herein, but rather to the data encoder associated with the transmission. The messages of the control channel and the voice channel shown in FIG. 1 in the AMPS mobile cordless telephone, as described in pages 138 to 141 of the magazine published by Bell Laboratories, are transmitted from the central processing unit (CPU) to the NRZ. It is output as (Nonreturn to Zero) data, and this NPZ data is manchester encoded as 10kbs wideband transmission data by a bit encoder circuit. Typically, a central processing unit (CPU) has been used an 8 bit microprocessor. Therefore, the Manchester encoder circuit needs to encode the 8-bit data output from the central processing unit, and the signaling tone when handing off or holding the signal when transmitting a signaling tone, ie, when handing off or holding. It should also be able to transmit the interrupt signal and interrupt signal to output the interrupt signal to program the peripheral device. In addition, mobile wireless telephones are mounted in automobiles, so they are required to be compact, lightweight, and low power. In addition, in the case of a mobile cordless mobile phone, the surrounding environment, that is, the conditions such as temperature, vibration, and humidity tend to change in a wide range, and it is desired to integrate an integrated circuit with high reliability and no malfunction.

Accordingly, an object of the present invention is to provide an encoder circuit capable of preventing malfunction and providing high reliability by constructing all of the wideband transmitters of a mobile wireless vehicle telephone with digital logic circuits.

It is still another object of the present invention to provide an encoder circuit that can be integrated circuitry and can provide small size, light weight, low power, and ease of mass production.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a block diagram of an encoder circuit which is a broadband data transmitter according to the present invention. In the drawing, the latch circuit 1 inputs the data input terminal 8 and the address of the various data messages and address decoder signals of FIG. 1 outputted in parallel by 8 bits from the above-described CPU (central processing unit), not shown. Input to terminal (9). It also functions to latch data messages output from the CPU in parallel in accordance with control signals input from the data or signaling tone control signal input terminal 7. In other words, when outputting data from the CPU, a logic signal indicating that the data is input to the input terminal 7 is input so that the latch circuit 1 latches the input parallel data and outputs the signaling tone. Reset the circuit (1).

The shift register 2 parallelizes the parallel data latched by the latch circuit 1 according to a 10 KHZ clock input to the clock input terminal 11 and a logic control signal output from the parallel load signal generator 6 described later. It loads in parallel and outputs the data loaded in parallel.

The transmit clock synchronization circuit 3 inputs a clock of 10KHZ input to the clock input terminal 11 and a transmit enable signal output from the CPU input to the transmit enable signal input terminal 10 to synchronize with the transmit clock. A signal for determining the time to transmit the transmission wideband data is generated at the output terminal Q, and when there is no input of the transmit enable signal, a signal for causing the parallel load signal generator 6 to output the parallel load signal is generated.

The interrupt signal generator 5 is set by inputting a path for determining the time for transmitting the transmission wideband data, and counts by inputting and counting a 10KHZ clock input to the clock input terminal 11 to interrupt the CPU interrupt signal during data transmission. Occurs with Le Andgate G36.

The parallel load signal generator 6 inputs the output of the interrupt signal generator 5 and the output of the 10 KHZ clock and the transmit clock synchronization circuit 3 to the shift register 2 when the transmit enable signal is input. A signal that causes the loaded parallel data to be output as serial data every 8 bits and the shift register 2 loads the 8-bit data latched to the latch circuit 1 in parallel when there is no input of the transmit enable signal. Occurs.

In addition, the Manchester encoder 4 outputs the Manchester encoded data by performing the Manchester encoding on the serial data output from the shift register 2 with a 10 KHZ clock.

The AND gate G36 outputs an interrupt signal whenever an 8-bit data is transmitted after the transmission start when the data control signal is input to the data or signaling tone control signal input terminal 7 and the transmit enable signal is input. Will output This interrupt signal interrupts the CPU to program peripheral circuits. Meanwhile, the AND gate G33 inputs a signaling tone control signal to the control signal input terminal 7, outputs a signaling tone of 10 KHZ, inputs a data control signal to the control signal input terminal 7, and starts transmission. Output to the output terminal 13.

는 "Q"의 상태가 된다.Therefore, in the present invention, a signal having a "high" state (hereinafter referred to as "1") to the input terminal 7 is inputted to the AND gate G36, and a transmit enable signal is inputted to the input terminal 10 and 10KHZ. Clock signal is input to the transmit clock synchronization circuit 3, and the output terminal Q of the transmit clock synchronization circuit 3 is in the state of " 1 "

Becomes the state of "Q".

Therefore, the AND gate G33 outputs the output signal of the retracted Manchester encoder 4 as it is.

On the other hand, the interrupt signal generator 5 inputs a signal having a state of "1" which is an output signal of the output terminal Q of the transmission clock synchronization circuit 3, sets the counter of the interrupt signal generator 5, A clock signal of 10 KHZ is input counted to output an interrupt signal of 100 mu sec for every 7 bits of Manchester encoded data described below to interrupt the CPU through the AND gate G36. On the other hand, the 8-bit parallel data output from the data output terminal of the CPU is input to the parallel data input terminal 8 of the latch circuit 1 and is input to the latch circuit 1 according to the address signal input to the address input terminal 9. It becomes a latch.

출력과 인테럽트 신호 발생장치(5)의 카운터의 출력을 입력하여 상기 인에이블 신호가 송신 클럭동기회로(3)에 입력하면 시프트레지스터(2)의 병렬신로로드 또는 직렬데이터 출력로드단자

에 직렬데이터 출력신호를 병렬로드 신호발생장치(6)에서 발생하고 상기 직렬데이터의 8번째 비트마다 50 μsec의 시간동안 상기 래치회로(1)에 래치된 데이터를 스프트레이스터(2)의 병렬입력에 로드시키고 다시 8비트의 데이터 신호를 시프트레지스터(2)의 출력단자(Q)로 출력시킨다.In addition, the transmission clock synchronization circuit 3

When the enable signal is input to the transmit clock synchronization circuit 3 by inputting the output of the output and the counter of the interrupt signal generator 5, the parallel path load or the serial data output load terminal of the shift register 2 is input.

A serial data output signal is generated by the parallel load signal generator 6, and the data latched to the latch circuit 1 is input in parallel to the latch circuit 1 for a period of 50 μsec for every eighth bit of the serial data. The 8-bit data signal is outputted to the output terminal Q of the shift register 2 again.

Therefore, the Manchester encoder 4 performs the Manchester encoding of the data signal output from the Spreader 2 according to the 10 KHZ clock, but delays the serial data output from the Shift Register 2 by 50 μsec. A Manchester encoded signal is output from the Manchester encoder 4 every 100 μsec so that the data of " 1 " and " 0 " appears in the down age, and is transmitted from the Manchester encoder 4 to the transmit wideband data output terminal 13 through the AND gate G33. Will be printed.

On the other hand, the transmitting unit of the mobile wireless vehicle should be able to transmit not only data but also a slewing tone (ST). At this time, the input terminal 7 is set to "0" to reset the latch circuit 1 to prevent data transmission. At the same time, if the output of the CPU interrupt signal is stopped by the AND gate G36 and the output signal of the output terminal Q of the transmission clock synchronization circuit 3 by the input of the enable signal TINA is "1", the 10KHZ clock The signaling tone by is outputted to the output terminal of the AND gate G33 through the Manchester encoder (4).

On the other hand, when no enable signal is input (for example, "0" state), the output terminal Q of the transmission clock synchronization circuit 3 is in the "0" state, and the output of the AND gate G33 is always in the "0" state. There is no sending out.

3 is an embodiment of the specific circuit diagram of the block diagram of FIG. 2 according to the present invention, the latch circuit 1, the shift register 2, the D-type flip-flops FF23 and FF28, and the T-type flip-flop FF24-FF27 and the exclusive noli. It consists of an exclusive or gate G32 and G34, an oragate G31 and an endgate G33, G35 and G36 and an inverter G37.

In the figure, the portion composed of the D flip-flop FF23 is the transmission clock synchronization circuit 3 of FIG. 2, and the portion composed of the exclusive OR gate G32 corresponds to the Manchester encoder 4, and the T-type flip-flop FF24-FF27 and the questionnaire. The portion composed of G35 corresponds to the interrupt signal generator 5, and the portion composed of the inverter G37, the D-type flip-flop FF28, the exclusive logic gate G34, and the oragate G31 correspond to the parallel load signal generator 6, respectively. .

4 is a timing diagram in each part of the concrete circuit diagram of FIG. 3 according to the present invention.

Hereinafter, the operation relationship of the concrete circuit diagram according to the present invention of FIG. 3 will be described in detail with reference to the timing diagram of FIG.

는 "1"상태가 출력하여 오아게이트 G31은 "1"상태가 출력하고 시프트레지스터(2)는 병렬로드 상태가 된다. 또한 앤드게이트 G33의 출력은 항상 "0"상태가 되어 송신 데이터의 출력은 없게 되며 T형 플립플롭 FF24-FF27로 구성되는 카운터는 리세트 상태가 되고 카운터의 출력단자들 Q24-Q27의 출력상태는 모두 "0"상태가 되어 제 4 도와 같이된다.When the transmit enable signal TINA of FIG. 4 is in the "0" state, that is, when no data is transmitted, the signal is inputted to the transmit enable input terminal 10 and a 10KHZ clock signal is inputted to the clock pulse input terminal 11. The output terminal Q23 of the D-type flip-flop FF23 operated by the above-described transmission clock synchronization circuit 3 outputs "0" and inverts the output terminal.

The state "1" is outputted, the OA gate G31 is outputted as "1" state, and the shift register 2 becomes a parallel load state. In addition, the output of the AND gate G33 always becomes "0" so that there is no output of the transmission data. The counter consisting of the T flip-flop FF24-FF27 is reset, and the output state of the counter output terminals Q24-Q27 All become "0" state and become 4th degree.

When data transmission is required, a signal of " 1 " state is inputted to the data / signaling tone input terminal 7, and the latch circuit 1 is set, and the CPU is provided to the data input terminal 8 and the address signal input terminal 9. 8-bit parallel data and an address signal are inputted from the latch, and the data is latched in parallel to the latch circuit 1. On the other hand, a transmit enable signal having a state of "1" is input to the transmit enable input terminal 10 of the D-type flip-flop FF23, which is a component of the transmit clock synchronization circuit 1, and a clock pulse of 10KHZ is input to the clock input terminal 11. Is inputted, and the waveform of the Q23 clock of FIG. 4 is output from the output terminal Q23 of the D flip-flop FF23 in synchronization with the 10 KHZ clock.

Therefore, when the transmit enable signal TINA is maintained at " 1 " state, the output signal of the exclusive logical sum gate G32, which becomes the Manchester encoder 4, appears at the output of the AND gate G33 and outputs to the transmission wideband data output terminal 13. .

In addition, by the signal of the output terminal Q23 of the D-type flip-flop FF23, a counter composed of the T-type flip-flops (FF24-FF27) of the interrupt signal generator 5 is set, and the 10KHZ clock pulses are counted up. The output terminals Q24-Q27 of the T-type flip-flop are output like the Q24 clock to Q2 clock waveforms of FIG.

에 입력하여 상기 래치회로(1)에 래치된 데이터를 시프트레지스터(2)의 병렬입력단자(P1-P8)에 입력로드 시킨다. 그리고 오아게이트 G31의 출력이 "0" 상태로 상기 스프트레지스터의 입력단자

에 입력하면 상기 병렬로드된 8비트 데이터는 시프트레지스터(2)의 출력단자(Q2)로 직렬데이터로 출력한다. 8비트 데이터의 예를 들어 파형도를 그린 것이 제 4 도의 시프트레지스터 Q2출력이며 첫번째 1바이트(8비트)의 데이터는 10110100임을 나타내고 있다.Therefore, the output of the output terminal Q27 of the T-type flip-flop FF27 of the counter is input to the D-type flip-flop FF28 in the parallel load signal generator 6, and after the clock pulse of 10KHZ is inverted by the inverter G37, the D It is inputted to the clock pulse input terminal of the type flip-flop FF28, and at the output terminal Q28, the output signal of the output terminal Q27 of the T-type flip-flop FF27 and a signal delayed by 50 μsec (Q4 clock Q28) are output, and both signals are exclusive. A pulse having a pulse width of 50 μsec input to the logic sum gate G34 appears as the output waveform of G34 in FIG. 4, and the output of the OR gate G31 is when the transmit enable signal is "0" and the output of the false exclusive logic gate G34 is " When it is 1 "state, it becomes" 1 "state, and this signal is the parallel, serial load signal input terminal of the shift register (2).

The data latched in the latch circuit 1 is inputted to the parallel input terminals P1-P8 of the shift register 2. And the input terminal of the sp register with the output of the OA gate G31 being " 0 ".

The 8-bit data loaded in parallel is output as serial data to the output terminal Q2 of the shift register 2. For example, a waveform diagram of 8-bit data is shown in the shift register Q2 output of FIG. 4, and the data of the first 1 byte (8 bits) is 10110100.

Accordingly, the shift register Q2 output signal of FIG. 4 is inputted to the exclusive logical sum gate G32, which becomes the Manchester encoder 4, with the 10KHZ clock pulse, and the output of the shift register Q2 output is the Manchester encoding (up). Data is displayed as one bit every 100 μsec with the age of “1” and the down age of “0”), and is output as the G33 output waveform of FIG. 4 through the AND gate G33 to the transmission broadband data output terminal 13.

On the other hand, the output signals of the output terminals Q24, Q25 and Q26 of the T-type flip-flop FF24-FF26 among the counters of the interrupt signal generator 5 are inputted to the AND gate G35 to output the D-type flip-flop FF23 by the transmit enable signal. After an output of 7 bits of the output signal of the terminal Q23 with the output signal of "1", the interrupt signal which becomes the "1" state with the time of about 100 microseconds after 50 microseconds after 7-bit output is sent through the AND gate G36. Output to the CPU interrupt output terminal 12.

On the other hand, in the case of a mobile wireless mobile phone, the transmitter should be able to transmit the signaling tone (ST) in addition to the data.

If this signal is " 0 ", the latch circuit 1 is reset and the AND gate G36 input is " 0 ", thereby preventing interruption. If the transmit enable signal is " 1 ", the clock of 10KHZ is Manchester Encoder. Input to exclusive logical sum gate G32 which is order (4), and output terminal Q2 of shift register outputs "0" state, so the clock of 10KHZ is output to exclusive logical sum gate G32, and the clock is also output to AND gate G33 and signaling tone is outputted. The transmission is output to the transmission broadband data output terminal 13.

As described above, the present invention can digitalize the entire circuit to send more accurate data, increase the reliability, and integrate the integrated circuit to reduce the cost by reducing the size, light weight, and reducing the production process. have.

Claims (4)

A transmitting circuit for encoding data output from a central processing unit of a mobile radio telephone, comprising: transmitting a transmit enable signal (TINA) output from the central processing unit and a clock pulse to convert the enable signal into the clock pulse; A set / reset according to the output of the transmission clock synchronizing circuit 3 and the transmission clock synchronizing circuit 3 and counting by inputting the clock pulses. An interrupt signal generator 5 for generating an interrupt signal every time and a serial load signal for inputting the count output and a clock pulse to generate a serial data output J signal and a parallel load signal for outputting a parallel load signal every 8 bits after transmission start The device 6 is inputted with data and address signals output from the central processing unit to set or re-set according to the data / signaling input signals. A latch circuit 1 for setting and latching the data, and parallelly loading the output data of the latch circuit 1 by the parallel load signal and a clock pulse and outputting the serial data by the serial data output generation control signal. An AND gate for inputting the shift register 2 and the clock pulse of the serial data of the shift register 2 to input the output of the Manchester encoding circuit to output transmission wideband data, and to output the clock pulse at the signaling tone output. And an AND gate (G36) for outputting the interrupt signal in accordance with a data / signaling signal of the interrupt signal of the interrupt signal generator (5). The interrupt signal generator (5) comprises a counter circuit composed of a plurality of T flip flops and a gate (G35) for inputting an output of the T flip flops to generate an interrupt signal. Circuit. The circuit according to claim 1, characterized in that the Manchester Star encoder (4) consists of an exclusive OR gate. 2. The D-type flip-flop FF28 according to claim 1, wherein the parallel load signal generator inputs a counting pulse and inputs a clock pulse, an exclusive logic sum gate 'G34' that outputs the counting pulse and an output thereof. And an orient (G31) for inputting the output of the transmission clock synchronous circuit (3) to output a parallel load or serial data generation control signal.

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