JPH02256341A - Synchronizing recovery circuit recovering word synchronization and radio communication equipment using the circuit - Google Patents

Abstract

PURPOSE:To speed up various processings of a radio communication equipment by processing both a received data signal and a word synchronizing signal representing its word synchronizing position as parallel data. CONSTITUTION:A forward control channel message is subject to FM demodulation by a receiver 1 and extracted by an LPF 13. A Manchester decoder 603 gives a Manchester code from data signal to a serial-parallel converter 604. The serial-parallel converter 604 converts a serial data from the Manchester decoder 603 into a 16-bit parallel data. The 16-bit output from the serial-parallel converter 604 is applied to a word synchronization detection circuit 611. The word synchronization detection circuit 611 detects a word synchronous character based on the data. Then the output signal of the word synchronization detection circuit 611 is read into a word synchronization detection shit register 621.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a synchronization recovery circuit and a wireless communication device using the same, and more specifically, to a synchronization recovery circuit and a wireless communication device using the same. The present invention relates to a synchronization recovery circuit that detects a word synchronization character to recover word synchronization, and to a wireless communication device such as a car phone or a mobile phone that uses such a synchronization recovery circuit.

(B) Prior Art Conventionally, cellular communication systems have been widely used as mobile radio telephones such as car phones and mobile phones. In such a cellular communication system,
The area to be covered is divided into a number of cells, and each cell is provided with a radio base station and assigned a group of channels. By keeping the coverage area of each cell small and reducing the transmission output of the base station, it is possible to frequently reuse frequencies and increase the number of subscribers.

In such a cellular communication system, when a mobile station equipped with a wireless communication device, such as a car equipped with a car telephone device, moves from one cell to another, the corresponding wireless base station and the corresponding In order to perform complete communication with the car telephone device, various digital controls such as channel changes are performed.

Each radio base station has two types of radio channels, one is a two-way control channel for various digital controls as mentioned above, and the other is a two-way voice channel for telephone conversations. be.

Four signal paths are used for such bidirectional communication. In other words, control channels include a forward control channel used for communication from a radio base station to each mobile station, a reverse control channel (RCC) used for communication from a mobile station to a radio base station, and mainly a voice channel. It was used for various controls before the establishment of
Not used for conversation. In addition, voice channels include a 7-Owned Voice Channel (FOVC) used for communication from a wireless base station to each mobile station, and a Reverse Voice Channel (RVC) used for communication from each mobile station to a wireless base station. There is.

In these channels, the message or data signal has a word synchronization character and is transmitted at a predetermined word rate and bit rate. Therefore, in a mobile station wireless communication device, it is necessary to first detect a word synchronization character from a received data signal to recover word synchronization. Therefore, in conventional wireless communication devices, for example, U.S. Patent No. 4,029,900
As disclosed in the above issue, a synchronization recovery circuit is provided which detects a word synchronization character from a data signal and recovers word synchronization, and this synchronization recovery circuit detects a word synchronization character from a data signal to recover a word synchronization signal based on the detected word synchronization character. is supplied to a data processing control circuit to restore word synchronization.

However, the conventional synchronization recovery circuit is configured to serially supply the word synchronization signal to the control circuit due to the node configuration. Therefore, in order to restore word synchronization based on such a serial word synchronization signal, the data signal must also be serially applied to the control circuit. The control circuit serially receives both the word synchronization signal and the data signal, and takes in and uses the data signal after the word synchronization position is determined as valid data. In such a configuration, if the data rate is high such as in a cellular communication system, data loss may occur if the data signal is read after word synchronization is established.

Therefore, the control circuit needs to constantly access data signals, and during that time cannot perform other processing such as key scanning, LCD display, AF (analog frequency) processing, and wireless function processing, which is necessary for the mobile station. There was a problem that various processes could not be performed at high speed.

In addition, in order to solve this problem, the control circuit is composed of two microprocessors, one of which performs synchronization recovery processing of received data, and the other performs other processing such as key scanning. This poses a problem in that complicated controls such as communication control (for example, communication protocol determination) and timing control between the two microprocessors are newly required.

On the other hand, a technology has been proposed that converts the data signal from serial to parallel and then supplies it to the control circuit.
No. 3-245032. however,
Since the word synchronization signal is supplied serially, it is impossible to confirm the synchronization position of the parallel data signal as it is, and some kind of software processing is required in the control circuit. Therefore, with such technology, it is difficult to operate the wireless communication device at high speed.

(c) Problems to be Solved by the Invention An object of the present invention is to speed up various processes of a wireless communication device in a cellular communication system.

Another object of the present invention is to enable recovery of word synchronization of received data by parallel signal processing in a wireless communication device serving as a mobile station.

(d) Means for Solving the Problems To summarize, the present invention converts serial data including a predetermined word synchronization character into first parallel data of n (n is an integer of 2 or more) bits, and 2nd bit of n bits indicating the word synchronization position in the parallel data of 1
parallel data is generated, and the word synchronization of the serial data is restored based on the first and second parallel data.

(E) Function The present invention is configured as described above, and both the received data signal and the word synchronization signal indicating the word synchronization position are processed as parallel data.

(F) Example An example of the present invention will be described below with reference to the drawings. Note that the embodiment described here uses the forward control channel (FO
This shows the case where the present invention is applied to CC). In this forward control channel, a forward control channel message (baseband data signal) is transmitted from a wireless base station, and the mobile station (wireless communication device) that receives this executes various processes such as registration and channel change according to the message. do.

FIG. 1 is a diagram showing a typical format of such a 7-year-old word control channel message. This message mainly consists of a bit synchronization field, a word synchronization field, and a data message. More specifically, the bit synchronization field, as shown in FIG. 2(a), is a 10-bit field in which 1's and 0's are alternately arranged (known as dotting). Next, the word synchronization field is an 11-bit field, as shown in FIG. 2(b), and has a bit arrangement that is unlikely to occur in voice messages. For example, in the United States, "11100010010" is shown in Figure 2 (b).
”.The data messages then include 40-bit data messages A and B each and are repeated 5 times in an alternating manner (each
represented as A1-A, and B, ~B). Repeating the data message five times in this way is for error correction, and when there is a discrepancy between the received data,
This is to determine the validity of the data based on a match of 15 or more, that is, based on majority vote.

Although not shown in FIGS. 1 and 2, one busy-idle bit is added for every 10 bits in the bit synchronization field, word synchronization field, and each data message. , this busy-idle bit is used to inform the mobile station of the acceptance state of the radio base station that is the source of the message, that is, the availability state of the reverse control channel (RCC). Therefore, the bit sync field,
The word sync field and data message will actually consist of 11 bits, 12 bits and 44 bits, respectively. In the United States, for example, the message shown in FIG. 1 is subjected to well-known Manchester encoding and transmitted at a rate of 10 kilobits/second.

Next, FIG. 3 is a schematic block diagram of a wireless communication device as a mobile station in a cellular system, which is an embodiment of the present invention. In FIG. 3, an antenna 3 is connected to a receiver 1 and a transmitter 2 through an antenna duplexer 4. Receiver 1 performs FM demodulation on a signal received by antenna 3 from a wireless station. Then, the receiver 1 uses a discriminator (not shown) to provide the 7-word control channel data signal to the data receiver 6, and also provides the received audio signal of the forward voice channel to the audio processing section 5. The data receiver 6 detects a word synchronization character from the applied FCC message and supplies the word synchronization signal together with the data signal to a control circuit 8 consisting of an 8-bit microprocessor. After confirming the synchronization position of the data signal based on the applied word synchronization signal, the control circuit 8 executes various controls according to the data signal.

The control circuit 8 also includes a key matrix 11 and an LC.
Performs necessary processing and control for the D driver 12 and the like. On the other hand, the audio processing unit 5 amplifies the received audio signal of the given FOVC and provides it to the speaker 10 of the handset. This allows the user of the mobile station to receive a call from the other party. Note that the control circuit 8 also controls the audio processing section 5, such as issuing a muting instruction.

The data transmitter 7 Manchester-encodes the data signal from the control circuit 8 and sends it to the transmitter 2 as an RCC message.
give to On the other hand, the audio processing section 5 processes the user's audio signal given via the microphone 9. It is given to the transmitter 2 as an RVC transmission audio signal. The transmitter 2 FM modulates these messages and transmits them via the antenna 3 to the base station.

Note that the radio base station of each cell is connected to a mobile telephone switching office (MTSO) (not shown) via a conventional land line or microwave network. The MTSO is also connected to the Public Switched Telephone Network (PSTN) and connects mobile radio telephones and
An interface with the STN is achieved.

Next, FIG. 4 is a block diagram showing the internal mechanism of the data receiver 6 shown in FIG. 3, and FIGS. 5 to 10 are block diagrams showing details of each part thereof. Also, the first
FIG. 1 is a timing chart showing each signal of the data receiver 6, and FIG. 12 is a diagram schematically explaining its operating principle.

First, a forward control channel message transmitted from a radio base station (not shown) is FM demodulated by the receiver 1 and extracted by the LPF 13. The analog forward control channel message extracted by the LPF 13 is digitized by a limiter 601 and then provided to a clock signal generation circuit 602 and a Manchester decoder 603 as a data signal in Manchester code format. The clock signal generation circuit 602 is a well-known PLL.
It is formed by a circuit and generates a clock signal RT (FIG. 11(b)) which is bit-synchronized with a data signal in Manchester code format. This clock signal RT is Manchester decoded! 603 and inverter 607 while
It is also applied to a delay circuit 608 and a word synchronization detection shift register 621, which will be described later. Further, the Manchester decoder @603 converts the Manchester code format data signal into an NRZ format data signal (il1 (a)) according to the data signal and the clock signal RT, and supplies the converted data signal to the serial-parallel converter 604. . This serial-parallel converter 604 has a function as a 16-bit shift register, and converts the serial NRZf'-9 from the Manchester decoder 603 into 16-bit parallel data.

FIG. 5 shows this serial-parallel converter 6.

4 is a diagram showing the configuration of No. 4. FIG. As shown in FIG. 5, the serial-parallel converter 604 is composed of two 8-bit shift registers 605 and 606, and the clock terminal of each shift register is connected to the output RT (11 Figure (C)) is provided. therefore,
Shift register 6.

5 and 606 both operate at the timing of 〒. That is, the shift register 605 sequentially reads the NRZ data at the timing of RT and provides the output Q, to the data input of the shift register 606. 606 also sequentially reads the output Q of the shift register 605 at the timing of RT.As a result, the NRZ data from the Manchester decoder 5603 is converted into 16-bit parallel data Q. The output 8-bit data Q.-Q, is given to both the delay circuit 608 and the word synchronization detection circuit 611, and the 8-bit data Q.-Q11 output from the shift register 606 is given to the word synchronization detection circuit 611. It will be done.

FIG. 6 is a diagram showing the configuration of the 8-bit shift register 605 or 606 shown in FIG. 5, and is composed of eight flips 70 connected in series.

Returning to FIG. 4, 1 of the serial-to-parallel converter 604
The 6-bit output is applied to word synchronization detection circuit 611. This word synchronization detection circuit 611 detects a word synchronization character based on these data. To explain in more detail, the word synchronization detection circuit 611
The 15-bit word synchronization character “1010 (bit synchronization field) 11 is composed of the last 4 bits of the 10-bit bit synchronization field shown in Fig. 2 and the 11-bit word synchronization field.
100010010 (word synchronization field)''.For boat fishing, the word synchronization character and lid may be configured only with the 10-bit word synchronization field, but as mentioned above, the original word synchronization field By adding the last 4 bits of the bit synchronization field to the 10 bits of the field to increase the number of bits of the word synchronization character, the probability that the word synchronization character coincidentally matches the data in the data message part is reduced, and the word synchronization The detection accuracy is increased.The output signal of the word synchronization detection circuit 611 is read into the word synchronization detection shift register 621 at the timing of the clock signal RT.

The fsr diagram is a diagram showing details of the word synchronization detection circuit 611 and the word synchronization detection shift register 621. In FIG. 7, the word synchronization detection circuit 611 is
It is composed of inverters 612 to 619 and an AND gate 620. The AND gate 620 outputs the outputs of the serial-to-parallel converter 604, Q, , Qi+k Q#*
Q + aw Ql, and Q 11 and the output Q
Or Q St Q l+ Q me Q @*Q?
+ Q m and Q are ANDed with the inverted signal. Note that the output Q11 of the serial-parallel converter 604 is the sea-idle bit as described above,
Since it is unrelated to word synchronization, this output Q II is AND
It is not connected to gate 620. Therefore, the outputs of serial-to-parallel converter 604 Q IS ~Q 11 and Ql. ~The value of Q0 is “101011100010010”, which is the 15-bit word synchronization character mentioned above.
”, the inputs of AND gate 620 are all “1'”, and AND gate 620 provides an output of “1” indicating the detection of a word sync character.

The output of this AND gate 620 is sequentially read into a word synchronization detection shift register 621, which is an 8-bit shift register, at the timing of the clock signal RT, that is, with a half-cycle delay relative to RT, as shown in FIG. Rarely,
It is converted into 8-bit parallel data WS0 to WS.

The 8-bit parallel data WS0 to WS are then applied to the word synchronization detection output port 22. The output port 22 simultaneously latches 8-bit input data at the timing of the output RT8 (FIG. 11(d)) obtained by dividing the output RT of the inverter 607 by 8 by the frequency divider 610.

On the other hand, the outputs Q, ~Q, of the 8-bit shift register 605 of the serial-parallel converter 604 are transmitted to the delay circuit 60.
given to 8. The delay circuit 608 is an 8-bit buffer register composed of eight flip-flops as shown in FIG. At the timing of signal RT, 8-bit data Q, ~Q,
read at the same time. That is, this 8-bit register 60
8 is a timing register provided for synchronizing with the word synchronization detection shift register 621. Then, the output of this shift register 608 RD e~RD
t is given to the received data output port 09. The output port 09, like the above-mentioned output port 22,
At the timing of RT8, which is the output of frequency divider @610, 8 pit input data are latched simultaneously.

Reading from output ports 09 and 622 is performed in response to address signals ARD and AWS from a 2-bit address line 624 and a read signal RD, and the output of each output port is transmitted via an 8-bit data bus 623. hand,
The signal is transmitted to the control circuit 8 shown in FIG.

FIG. 9 is a block diagram showing details of these output ports 09 and 622. In FIG. 9, the output port 09 is the 8-bit output RD, ~RD of the delay circuit 608 at the timing of the clock RT8 from the frequency dividing circuit 610.
, and the read data is read by the read signal R.
D and address signal ARD, the data is read out to 8-bit data bus 623 as 8-bit data signals D0-D. In addition, the output port 22 also has a clock R.
It includes an 8-bit three-state buffer register 622a that latches the 8-bit outputs WS0 to WS of the word synchronization detection shift register 621 at the timing of T8, and the read data is output by the read signal ■ and the address signal A.
WS and is read out to the 8-bit data bus 623 as an 8-bit data signal.

FIG. 10 is a diagram showing the configuration of the Srini state buffer register 609α or 622ω in FIG. 9, which includes eight flip-flops provided in parallel and a gate provided for each Q output of the flip-flop. We are prepared. To prevent short circuits through the 8-bit data bus 623, output ports 09 and 622 open their gates only when output activation is commanded sequentially at different times, and the data in the buffer register is read onto the data bus 623. is configured to be

FIG. 12(a) shows the received data output ports 09 to 8.
12(b) shows the NRZ data that is output in parallel for each bit.
It shows word synchronized data that is output in parallel every 2 to 8 bits. As is clear from the above description and FIG. 12, the synchronization data output from the output port 22 has a word synchronization confirmation flag 1'' at a position corresponding to the word synchronization position in the output signal from the output port 09.

Next, FIG. 13 is a diagram showing the connection relationship between the control circuit 8 of FIG. 3 and its peripheral units, and this control circuit 8 is realized by a microcomputer as shown in FIG. 13. The control circuit 8 receives the clock “
In addition to receiving 〒1 as an interrupt request, the data bus 62
3, receives the above-mentioned 8-bit reception data or synchronization data D, -D. The control circuit 8, on the other hand, provides the aforementioned address signals π11 and TW3 to the data receiver 6 via a 2-bit address line 629.

The control circuit 8 also has the aforementioned output ports 09 and 62.
A read signal RD for 2 is provided. Furthermore, the control circuit 8 supplies necessary signals to the audio processing section 5, the data transmission a7, and the LCD driver 12 to control their operations,
Furthermore, the operation of the key matrix 11 is monitored.

Next, FIG. 14 is a flowchart illustrating the operation of the control circuit 8. The operation of the control circuit 8 will be described below with reference to FIGS. 13 and 14.

First, the control circuit 8 resets the flag register F (not shown) (step 5-1), and determines whether there is an interrupt request based on the output signal RT8 from the frequency divider 610 in the data receiver 6. (Step 5-2). If requested, other processes such as key scanning, LCD driving, and audio processing are interrupted and the 8-bit received data sent from the data receiver 6 via the data bus 623 (see FIG. )) and 8-bit synchronized data (Fig. 12(b)
) is read (step 5-3). Then, it is determined whether or not the read 8-bit synchronization data includes a word synchronization confirmation flag 1'' as shown in FIG. 12(b).
Step 5-4), if not, return to step S-2 via step S-9.

On the other hand, if it is determined in step S-4 that the word synchronization confirmation flag is included in the synchronization data, the bit position of the flag is further detected (step 5-5).
, the received data after that bit position is stored in the memory in the control circuit 8 as valid data (step 5-6).
). In this way, once word synchronization is established, a flag is set in the aforementioned flag register F (step 5).
-7).

Thereafter, when there is an interrupt request (step 5-2), the received data is stored in the memory regardless of the presence or absence of the word synchronization confirmation flag (steps S-6, S-1O), and the reading of all received data is completed. Then (step S-11), data processing such as busy-idle bit deletion and error correction is executed (step S-12). In addition, step 5
The completion of reading at -11 can be determined by providing a word counter that is incremented each time one word (8 bits) of data is taken in and monitoring the count value.

Next, FIG. 15 is a flowchart showing another example of the processing of the control circuit 8. In the example shown in FIG.
As shown in the figure, all data bits are stored in the memory in the control circuit 8, with one-to-one correspondence (
Step S-22). After the reading is completed, step S detects the position where the word synchronization confirmation flag is "1".
-23, 24), various data processes are executed using the received data after the detected flag position among the stored data (step S-25). In the above-described embodiment, the present invention was applied to recovery of word synchronization in the reception system of forward control channel messages, but the above-mentioned circuit can also be applied to recovery of synchronization of messages on the forward voice channel. It is possible to apply this using a circuit with the same configuration as .

(g) Effects of the Invention As described above, the present invention processes both the word synchronization data indicating the word recovery position and the received data as parallel data, so that word synchronization can be quickly recovered. In turn, it becomes possible to perform various types of processing as a wireless communication device at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a typical format of a forward control channel message. Figure 2(a)
and (b) are diagrams showing specific examples of a bit synchronization field and a word synchronization field, respectively. Third
FIG. 1 is a schematic block diagram showing a wireless communication device that is an embodiment of the present invention. FIG. 4 is a block diagram showing the internal configuration of the data receiver in the wireless communication device shown in FIG. 3. FIG. 5 is a diagram showing details of the serial-parallel converter shown in FIG. 4. FIG. 6 is a block diagram showing details of the 8-pit shift register shown in FIG. 5. FIG. 7 is a block diagram showing details of the word synchronization detection circuit and word synchronization detection shift register shown in FIG. 4. FIG. 8 is a block diagram showing details of the delay circuit shown in FIG. 4. FIG. 9 is a block diagram showing details of the received data output port and word synchronization detection output port shown in FIG. 4. FIG. 10 is a block diagram showing the configuration of the three-state buffer register shown in FIG. 9. FIG. 11 is a timing chart illustrating the operation of the circuit shown in FIG. 4. FIG. 12 is a diagram schematically explaining the operating principle of the circuit shown in FIG. 4. FIG. 13 is a block diagram showing details of the control circuit shown in FIG. 3. FIG. 14 is a flowchart illustrating the operation of the microcomputer shown in FIG. 13. FIG. 15 is a flowchart showing another example of the processing of the microcomputer shown in FIG. 13. (1)...Receiver, (2)...Transmitter, (6)...
・Data receiver, (7)...Data transmitter, (8)・
...Control circuit. Applicant: Sanyo Electric Co., Ltd. and one other person Agent: Patent attorney Takuji Nishino (two others) Figure 1 Figure 2 Figure 5 = Figure 9 Figure 1 Figure 1 Figure 1 Figure 2 b. b. b. b. b. b. b! b. b. b. b. b. Confirmed flag Fig. 3 Fig. 1 4

Claims (36)

[Claims] (1) In a synchronization recovery circuit that recovers word synchronization of serial data including a predetermined word synchronization character, the serial data is
data conversion means (604) for converting into parallel data of
, synchronous data generating means (604, 611, 621) for generating n-bit second parallel data indicating a word synchronous position in the first parallel data;
and a control means (8) for restoring word synchronization of the serial data based on the second parallel data. (2) The data conversion means converts the serial data into
first serial data that is converted into the first parallel data at the timing of a predetermined first clock signal (@RT@);
The synchronization data generation means includes a parallel conversion means (605), and the synchronization data generation means converts the serial data into a third m (m is an integer) bit corresponding to the number of bits of the synchronization character at the timing of the first clock signal. a second serial-to-parallel conversion means (605
, 606) and means for determining that the third parallel data matches the predetermined word synchronization character (
611), and a third serial-to-parallel conversion means (611) for converting the output of the coincidence determination means into the second parallel data at the timing of a second clock signal (RT) obtained by delaying the first clock signal. 621). 621). The synchronization recovery circuit according to claim 1. (3) A patent claim further comprising a delay means (608) for latching the first parallel data output from the first serial-parallel conversion means at the timing of the second clock signal. The synchronization recovery circuit according to item 2. (4) A first latch means that latches the first parallel data output from the delay means at the timing of a third clock signal (@RT8@) obtained by dividing the first clock signal by n. 609) and the third serial-
Claim 3, further comprising a second latch means (622) for latching the second parallel data output from the parallel conversion means at the timing of the third clock signal. synchronization recovery circuit. (5) The control means executes an interrupt process to read first and second parallel data latched in the first and second latch means, respectively, in response to the third clock signal. 5. A synchronization recovery circuit according to claim 4, characterized in that it comprises means. (6) The synchronization recovery circuit according to claim 5, wherein the first and second parallel data are read into the control means at different timings. (7) The synchronization recovery circuit according to claim 5, wherein the control means executes processes other than word synchronization recovery at times other than when executing the interrupt process. (8) The control means includes a storage means and the read second
means for determining whether or not a synchronization confirmation bit indicating a word synchronization position is included in the parallel data of the first parallel data; 6. The synchronization recovery circuit according to claim 5, further comprising means for storing data subsequent to the bit corresponding to the synchronization confirmation bit as valid data in the storage means. (9) The control means includes a storage means and the read first
and means for storing second parallel data in the storage means with respective data bits in one-to-one correspondence, and synchronization indicating a word synchronization position in the second parallel data stored in the storage means. means for determining whether or not a confirmed bit is included; and when it is determined that the synchronization confirmed bit is included, a means for determining whether or not the synchronization confirmed bit is included; 6. The synchronization recovery circuit according to claim 5, further comprising means for using the data as valid data in data processing. (10) The first serial-to-parallel conversion means has n
3. The synchronization recovery circuit according to claim 2, further comprising a bit shift register. (11) The second serial-to-parallel conversion means is m
3. The synchronization recovery circuit according to claim 2, further comprising a bit shift register. (12) The synchronization recovery circuit according to claim 2, wherein the coincidence determination means includes logic circuit means having m inputs. (13) The third serial-to-parallel conversion means has n
3. The synchronization recovery circuit according to claim 2, further comprising a bit shift register. (14) The synchronization recovery circuit according to claim 3, wherein the delay means includes an n-bit buffer register. (15) The synchronization recovery according to claim 4, wherein the first and second latch means each include an n-bit three-state buffer register whose reading is controlled by the control means. circuit. (16) The synchronization recovery circuit according to claim 1, wherein the serial data is a forward control channel message in a cellular communication system. (17) The synchronization recovery circuit according to claim 1, wherein the serial data is a forward voice channel message in a cellular communication system. (18) In a wireless communication device having at least a function of receiving data transmitted from a wireless base station, means (3, 4, 1) for receiving and demodulating the transmitted data, a predetermined word from the received data; Means for extracting serial data including synchronization characters (13, 601, 602
, 603), and synchronization recovery means for restoring word synchronization of the serial data, wherein the synchronization recovery means converts the serial data into n (n is an integer of 2 or more) bits of first parallel data. data converting means (604) for converting, and synchronization data generation means (604, 611, 621) for generating n-bit second parallel data indicating a word synchronization position in the first parallel data;
A control means (8) for restoring the word synchronization of the serial data based on the first and second parallel data, and performing necessary processing based on the data in which the word synchronization has been restored. wireless communication equipment. (19) The data conversion means includes a first serial-to-parallel conversion means (605) that converts the serial data into the first parallel data at the timing of a predetermined first clock signal (@RT@). and the synchronous data generating means converts the serial data into third parallel data of m bits (m is an integer) corresponding to the number of bits of the synchronous character at the timing of the first clock signal. serial-to-parallel conversion means (605
, 606) and means for determining that the third parallel data matches the predetermined word synchronization character (
611), and a third serial-to-parallel conversion means (611) for converting the output of the coincidence determination means into the second parallel data at the timing of a second clock signal (RT) obtained by delaying the first clock signal. 621). The wireless communication device according to claim 19. (20) Delay means (608) for latching the first parallel data output from the first serial-parallel conversion means at the timing of the second clock signal.
Claim 19, further comprising:
The wireless communication device described in Section 1. (21) The first parallel data output from the delay means is divided into a third clock signal by dividing the first clock signal by n.
The first latch means (609) latches the second parallel data output from the third serial-to-parallel converter at the timing of the clock signal (@RT8@), and the second parallel data is latched at the timing of the third clock signal (@RT8@). 21. The wireless communication device according to claim 20, further comprising a second latch means (622) that latches at a timing. (22) The control means executes an interrupt process for reading first and second parallel data latched in the first and second latch means, respectively, in response to the third clock signal. 22. A wireless communication device according to claim 21, characterized in that it comprises means. (23) The wireless communication device according to claim 22, wherein the first and second parallel data are read into the control means at different timings. (24) The wireless communication device according to claim 22, wherein the control means executes processing other than word synchronization recovery at times other than when executing the interrupt processing. (25) The control means includes a storage means, a means for determining whether a synchronization confirmation bit indicating a word synchronization position is included in the read second parallel data, and a means for determining whether the synchronization confirmation bit indicates a word synchronization position. If it is determined that the
23. The wireless communication according to claim 22, further comprising means for storing data subsequent to the bit corresponding to the synchronization confirmation bit in the first parallel data as valid data in the storage means. Device. (26) The control means includes a storage means, a means for causing the read first and second parallel data to be stored in the storage means in a one-to-one correspondence of data bits, and the storage means means for determining whether or not a synchronization confirmation bit indicating a word synchronization position is included in the second parallel data stored in the second parallel data; 23. The wireless communication apparatus according to claim 22, further comprising means for using data after the bit corresponding to the synchronization confirmation bit in one parallel data as valid data for data processing. (27) The wireless communication device according to claim 19, wherein the first serial-to-parallel conversion means includes an n-bit shift register. (28) The wireless communication device according to claim 19, wherein the second serial-to-parallel conversion means includes an m-bit shift register. (29) Claim 19, wherein the coincidence determination means includes logic circuit means having m inputs.
The wireless communication device described in Section 1. (30) The third serial-to-parallel conversion means has n
20. The wireless communication device according to claim 19, further comprising a bit shift register. (31) The wireless communication device according to claim 20, wherein the delay means includes an n-bit buffer register. (32) The wireless communication according to claim 21, wherein the first and second latch means each include an n-bit three-state buffer register whose reading is controlled by the control means. Device. (33) The wireless communication device according to claim 18, wherein the serial data is a forward control channel message in a cellular communication system. (34) The wireless communication device according to claim 18, wherein the serial data is a forward voice channel message in a cellular communication system. (35) The wireless communication device according to claim 18, further comprising audio processing means (5) for extracting and processing data including an audio signal from the received data. (36) The wireless communication device according to claim 35, further comprising means (2, 7) for receiving data from the control means and the audio processing means and transmitting it to the wireless base station.