JP3182312B2 - Wireless communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a wireless communication device such as a cordless phone, a cellular car phone, and a mobile phone which can receive a data signal transmitted at a bit rate and including a predetermined synchronization character.

[0002]

2. Description of the Related Art Conventionally, in a cellular communication system, a baseband data signal (forward control channel message) for controlling a channel change or the like is transmitted from a radio base station and received by a radio communication device. To perform each process.
By the way, this baseband data signal has a word synchronization character and is transmitted at a predetermined word rate and a predetermined bit rate. The wireless communication apparatus first detects the word synchronization character and recovers the word synchronization. There is a need. Therefore, as disclosed in, for example, Japanese Patent Application Laid-Open No. 52-115609, a data signal recovery circuit is provided, and a word synchronization signal is supplied to a data processing control circuit upon detection of the word synchronization character. .

[0003]

Incidentally, since word correction characters are not usually included in word synchronization characters, burst errors due to fading or the like or lack of word synchronization due to random errors in a weak electric field area are likely to occur. Here, a practical problem is a random error in a weak electric field area.

The synchronization signal recovery circuit compares a predetermined word synchronization pattern with a word synchronization character received by the wireless communication device and attempts to match them. If a random error occurs, word synchronization is lost. Here, an allowable value is provided for error information generated when a predetermined word synchronization pattern is compared with a word synchronization character received by the wireless communication device, and when the error information is less than the allowable value, word synchronization is determined. However, in this case, the fact that this method is used even in a field strength area sufficient to receive the word synchronization character has a disadvantage that the possibility of erroneous word synchronization increases. .

[0005]

According to the present invention, there is provided a radio communication apparatus comprising: measuring means for measuring a received electric field strength; error determining means for determining an allowable error number of the word synchronization character based on the measuring means; When it is detected that the word synchronization pattern completely matches with the word synchronization pattern, the synchronization determination flag is set. With the synchronization determination flag set, the number of errors in the input data for the word synchronization pattern is determined by the allowable error determined by the determination means. A synchronization recovery means for canceling the synchronization determination flag when the number exceeds the number.

[0006]

Since the present invention is constructed as described above, the word synchronization character is detected in accordance with the radio wave condition, and a stable synchronization state can be maintained.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. The embodiment described here shows a case in which a forward control channel (FOCC) is applied to the present invention. In this forward control channel, a forward control channel message (baseband data signal) is transmitted from the wireless base station, and the mobile station (wireless communication device) receiving the forward control channel message executes various processes such as registration and channel change according to the message. I do.

FIG. 1 is a diagram showing a typical format of such a forward control channel message. This message is composed of a bit synchronization field, a word synchronization field, and a data message. More specifically, as shown in FIG. 2, the bit synchronization field is a 10-bit field, and 1 and 0 are alternately arranged (so-called dotting). Next, as shown in FIG. 3, the word synchronization field is an 11-bit field, and has a bit arrangement that hardly occurs in a voice message. For example, in the United States, as shown in FIG.
1100010010 "is set. Next, each data message has 40 characters.
Bit data messages A and B, each of which is repeated alternately 5 times (A1 to A, respectively)
5 and B1-B5). The reason why the data message is repeated five times in this way is to determine the validity of the data by a match of 3/5 or more, that is, by majority decision when there is a difference between the received data.

Although not shown in FIGS. 1 to 3, in the bit synchronization field, the word synchronization field and each data message, one for every ten bits is set.
Bit busy-idle bit is added. This busy-idle bit is for notifying the mobile station of the acceptance state of the radio base station that is the source of the message, that is, the idle state of the reverse control channel (RECC). Therefore, the bit synchronization field, the word synchronization field and the data message actually consist of 11 bits, 12 bits and 44 bits, respectively. The message shown in FIG. 1 is, for example, in the United States, subjected to a well-known Manchester code, and transmitted at a rate of 10 kilobits / second. However, in order to simplify the description, the busy-idle bit is omitted in the following description.

Next, FIG. 4 shows a radio communication apparatus as a mobile station in the cellular system, wherein (1) and (2) are transmission and reception sections, which are a transmission / reception duplexer (3), a control signal, and speech coding. TDMA that performs time division multiplexing / demultiplexing of signals and synchronization signals
It is connected to a circuit (4) and implements basic wireless communication between the subscriber and a wireless base station (not shown). A radio link connection for communicating with a mobile telephone exchange (not shown) through a radio base station is formed, and an interface with a public telephone communication network is performed through the radio link connection. The transmission unit (1) is π /
It consists of a 4-shift QPSK modulator (5) and a highly efficient linear power amplifier (6). The receiving unit (2) includes a first receiving circuit (7) connected to the duplexer (3), a second receiving circuit (9) connected to the antenna (8), and a demodulator (1).
0), the demodulator (10) has a circuit for detecting the received electric field strength based on the received signals of the first receiving circuit (7) and the second receiving circuit (9), and the first receiving circuit There is also a diversity circuit that switches between (1) and the output of the second receiving circuit (9) at a predetermined timing and selects the one with the better receiving condition. (11) is a synthesizer circuit,
A carrier is supplied to the transmission unit (1), and a local oscillation signal is supplied to the first reception circuit (7) and the second reception circuit (9) of the reception unit (2), and the channel is changed by changing these frequencies. Will be. (12) is a voice codec, which codes and decodes a voice signal and has an error correction function for reducing the effects of fading and the like. (1
3) (14) are a microphone and a speaker, which are connected to the voice codec (12). (15) is a control circuit composed of a 16-bit microprocessor and an ASIC. The TDMA circuit (4), the word synchronous phase memory (1)
6), a display (17) for displaying a telephone number, a buzzer (18) for sounding a ring tone when an incoming call is received, and a key circuit (19). This control circuit (15)
The data from the TDMA circuit (4) is input to perform word synchronization recovery processing. In this processing, error information corresponding to the delay or advance of the received word synchronization with respect to the predicted word synchronization position is converted to word synchronization. Phase memory (1
6). Also, it analyzes a message from the wireless base station and controls various functions as a telephone device such as control of a wireless line and control of transmission output.

Next, FIGS. 5 to 8 show control circuits (1) related to reception of a forward control channel message.
5 is a flowchart of the program written in 5), FIG. 5 shows an outline of the overall operation, FIG. 6 shows a process of setting the allowable number of errors based on the received electric field strength of FIG. 5, and FIG. 7 shows an error information memory of FIG. It is a flowchart showing the processing in detail.

In FIG. 5, a control circuit (15) for a mobile station
First, the receiving channel is set (S1), and the TDM
The reception of data from the A circuit (4) is started (S2).
The received serial data is sequentially transferred to a 16-bit shift register, and the input data is shifted one bit at a time (S3). This shift register is used for determining synchronization, and input data is sequentially stored in a separate data processing memory. In the early stage of reception, since the synchronization has not been determined, the data in the shift register is compared with the word synchronization pattern, and data is received until a word synchronization character is detected without error (S4, S5). If the word synchronization character is detected without error, the reference value A of the received field strength (RSSI) for determining the allowable number of errors in the word synchronization detection is set to -115 dB (S6). This is-
Since it is defined that the word synchronization character must be detected without error at an electric field strength of 113 dB, the reference value is set to -115 dB, which is lower by 2 dB. Thereafter, the control circuit (15) sets a synchronization determination flag (S7), presets a built-in synchronization waiting counter (S8), and starts counting of the synchronization waiting counter (S9). This synchronization wait counter counts the number of bits of input data after the synchronization position.
Since the forward control channel message has 421 bits (excluding the busy-idle bit) as a whole as described above, the next time logically, the synchronization position is reached when 421 counts are performed. Is preset to the synchronization wait counter.

Next, the processing of steps 2 and 3 is performed until the synchronization wait counter counts over, and the data processing of the data message is performed (S4, 10, 11).
In the data processing of the data message, data after the synchronization determination bit is read from the data processing memory, and the data processing is sequentially performed. If the synchronization wait counter has counted over (Y in S10), the control circuit (15) measures the reception electric field strength of the reception channel,
The allowable value of the error information of the word synchronization character is set based on the received electric field strength (S13).

The error allowable value setting process will be described with reference to FIG. First, the control circuit (15) determines whether or not the measured received electric field strength is equal to or higher than the reference value A (S18). If the value is equal to or more than the reference value A, the allowable number of errors is set to “0” (S1
9) If it is less than the reference value A, it is determined whether or not it is equal to or greater than a value obtained by subtracting 2 dB from the reference value A (S20). If (A-
2) If the number is equal to or more than 1, the allowable number of errors is set to “1” (S2
1) If it is less than (A-2), it is determined whether or not it is equal to or more than a value obtained by subtracting 4 dB from the reference value A (S22). If (A-4) or more, the allowable number of errors is set to “2” (S23),
If it is less than (A-4), it is determined whether or not it is equal to or greater than a value obtained by subtracting 6 dB from the reference value A (S24). If (A-6) or more, the allowable number of errors is set to "3" (S25), and (A-
If less than 6), the allowable number of errors is set to “4” (S
26).

After the error allowable value setting processing, the control circuit (1
5) The detection process of the number of error information corresponding to the phase difference of the received data is performed (S14).

The detection process will be described with reference to FIG. First, the control circuit (15) sets the number of shift stages of the word synchronization pattern with respect to the data set in the shift register in order to detect the coincidence of the synchronization pattern from the data set in the shift register (here, five stages are set). (Set) (S27), and EOR the shift register data and the word synchronization pattern (S28). The error information obtained as a result (EOR error result is "1") is counted (S29), and the synchronization word predicted position (42 after the synchronization is determined) is counted.
The number of error information is stored in an area of the word synchronous phase memory (16) corresponding to the difference (phase difference) from the first bit (S3).
0). Thereafter, the word synchronization pattern is shifted by one stage (S3
1), S30 to S33 until the set shift stage number is reached
Is repeated (S32). Note that the phase difference is “−3”, “−”
2 "," -1 "," 0 "," 1 ", and" 2 "(see FIG. 8).

After this detection processing, the control circuit (15) sorts the data in the word synchronous phase memory (16) in ascending order of error information (S15), A comparison is made with the error allowable value determined by the setting process (S13) (S1).
6). Incidentally, the sorting of the word synchronous phase memory (16) is generally performed by a well-known technique without changing the area of the memory, but by controlling a pointer corresponding to the area. In addition, sorting is performed in the order of smaller error information by such a method, and if the number of error information is the same as a result of the execution, sorting is performed in the order closer to the synchronization prediction position (smallest phase difference). I have.

If the result of the comparison is within the allowable error value, the above-described steps S7 to S9 are repeated (S16).
If the error allowable value is exceeded, the synchronization determination flag is released (S17).

[0019]

As described above, the present invention reduces the allowable number of word synchronization errors where the received electric field strength is high,
In a place where the reception electric field strength is weak, by increasing the allowable number of errors of word synchronization due to random errors and saving the detection of word synchronization having no error correction code, it is possible to maintain a stable synchronization state according to the radio wave state. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a typical format of a forward control channel message.

FIG. 2 is a diagram showing a specific example of a bit synchronization field.

FIG. 3 is a diagram showing a specific example of a word synchronization field.

FIG. 4 is a block diagram of a wireless communication device according to the present invention.

FIG. 5 is a flowchart of a program related to reception of a forward control channel message written in a control circuit of a wireless communication layer according to the present invention.

FIG. 6 is a flowchart showing a setting process of an allowable number of errors based on a received electric field strength in the flowchart of FIG. 5;

FIG. 7 is a flowchart showing an error information memory process in the flowchart of FIG. 5;

FIG. 8 is a diagram illustrating a method of detecting a word synchronization character.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmitting part 2 Receiving part 4 TDMA circuit 12 Voice codec 15 Control circuit 16 Word synchronous phase memory

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-327688 (JP, A) JP-A-60-9241 (JP, A) JP-A-52-115609 (JP, A) JP-A-4- 63028 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 7/26 H04J 3/06 H04L 7/00 H04L 7/08 H04L 27/22

Claims (1)

(57) [Claims] 1. A method for recovering word synchronization of serial data including a predetermined word synchronization character and receiving a data message, comprising: measuring means for measuring a received field strength; and permitting the word synchronization character based on the measuring means. The error determination means for determining the number of errors, and when it is detected that the input data completely matches the word synchronization pattern, a synchronization determination flag is set, and the synchronization determination flag is set.
In the state, the input data error for the word synchronization pattern
The number has exceeded the allowable error number determined by the determination means.
A wireless communication device comprising: a synchronization recovery unit configured to release the synchronization determination flag .