JPH05268207A - Frame synchronization system - Google Patents

Abstract

PURPOSE:To prevent the influence of a frequency division clock phase at the time of executing conversion to n-string of parallel signal strings. CONSTITUTION:A parallel converting circuit 1 converts a digital signal string Di into the n-string of parallel signal strings in accordance with an input clock C1 so as to transmit them to signal lines 101-10n and also to output a frequency division clock C2. Frame synchronizing circuits 11-1n are provided so as to respectively correspond to the n-kinds of frame synchronization pattern arrangements of the parallel signal strings, respectively receive the parallel signal and the frequency division clock C2 and transmit frame synchronization establishment information S1-Sn at the time of establishing a frame synchronization. A phase detecting circuit 3 outputs phase information A1 such as the digital signal string and the frequency division clock C2 in accordance with frame synchronization establishment information from the frame synchronizing circuit, where the frame synchronization is established, and with the input clock. The parallel converting circuit 2 converts the digital signal string Di into the n-number parallel signal strings being prescribed arrangements accordance with phase information A1 and the input clock C1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system, and in particular, it establishes frame synchronization for a digital signal sequence including a frame synchronization pattern composed of a plurality of data and parallels n columns (n is an integer of 2 or more) in parallel. The present invention relates to a frame synchronization system for transmitting as a signal train.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional frame synchronization system for converting a digital signal train into n (where n is an integer of 2 or more) parallel signal trains for output.

The parallel conversion circuit 21 divides the digital signal sequence Di by n in accordance with the input digital signal sequence Di and the input clock C1 synchronized with this digital signal sequence to convert it into n parallel signal sequences, and then n. Column signal lines 101 to 1
The frequency-divided clock C2 is output while being sent to 0n.

The n frame synchronization circuits 11 to 1n are n
N of the parallel signal train sent to the signal lines 101 to 10n of the train
When the individual frame synchronization is established, the frame synchronization establishment information S1 is provided when the parallel signal sequences and the divided clocks C2 from the n columns of the signal lines 101 to 10n are respectively provided corresponding to the different frame synchronization pattern arrays. ~ S
n are sent respectively.

The phase detection circuit 23 detects the phase of the divided clock C2 from the frame synchronization establishment information S1 to Sn,
Rearrangement information A2 for rearranging into a predetermined arrangement is generated and transmitted. The alignment circuit 22 rearranges the parallel signal trains of the n-column signal lines 101 to 10n into a predetermined array according to the rearrangement information A2, and outputs the n-column output signal lines 201 to 20n.
Send to.

Next, the operation will be described.

For example, if the frame synchronization pattern is F1, F
2, ..., F8 digital signal train Di is converted into eight parallel signal trains, and output signal lines 201 to 208 respectively
It is assumed that the predetermined array of F1, F2, ..., F8 is transmitted.

By the way, when the parallel conversion circuit 21 converts into n parallel signal trains, there are eight parallel signal arrays due to the phase of the frequency division lock C2. Now, Fig. 5
As shown in, the array sent from the parallel conversion circuit 21 to the output signal lines 101 to 108 of eight columns is F4, F5, F.
6, F7, F8, F1, F2, F3.

Here, the frame synchronization circuit 11 provided corresponding to each of the eight types of frame synchronization pattern arrays.
Only the frame synchronization circuit corresponding to the arrangement of F4, F5, ..., F3 can establish the frame synchronization. For example, if only the frame synchronization circuit 14 establishes frame synchronization, the frame synchronization circuit 14 sends out the frame synchronization establishment information S4.

The phase detection circuit 23 arranges the arrays F4, F5, ..., F3 based on the frame synchronization establishment information S4.
Sorting information A2 for sorting in the order of 1, F2, F3, F4, F5, F6, F7, F8 is generated. The sorting circuit 22 sorts based on the sorting information A2,
The parallel signal train having the predetermined array F1, F2, ..., F8 is sent to the output signal lines 201 to 208. In this way, the parallel signal sequence is constantly rearranged so as to have a predetermined arrangement based on the frame synchronization establishment information.

[0011]

In the above-mentioned conventional frame synchronization system, the parallel signal train is constantly rearranged so as to have a predetermined arrangement based on the frame synchronization establishment information. However, when the device power is turned on or when re-frame synchronization is established due to the loss of frame synchronization of the signal sequence, the maximum time for frame synchronization to be established is n times for the digital signal sequence due to the indeterminacy of the phase of the divided clock. A variable delay of -1 bit shift occurs.

For this reason, for example, in a digital communication in which a single protection line is provided for a plurality of working lines and which performs non-instantaneous synchronization switching, when a conventional frame synchronization system is applied, the allowable variation delay value or more is exceeded. Since the signal train fluctuates, there is a problem in that it is not possible to perform non-instantaneous sync switching.

An object of the present invention is to convert a digital signal train into n parallel signal trains so that it is not affected by the phase of the divided clock and a variable delay due to phase uncertainty can be eliminated. It is to provide a synchronization system.

[0014]

In the frame synchronization system of the present invention, a digital signal sequence including a frame synchronization pattern composed of a plurality of data is frame-synchronized with n parallel signal sequences (n is an integer of 2 or more). In a frame synchronization system for conversion, the digital signal sequence is frequency-divided by n according to an input clock to be converted into a first parallel signal sequence of n lines, and at the same time, a first parallel conversion for outputting a first frequency-divided clock. Means and the first parallel signal train and the first parallel signal train and the first frequency-divided clock, respectively. From n frame synchronization means for establishing frame synchronization by a signal sequence and transmitting frame synchronization establishment information respectively, and the frame synchronization means for establishing frame synchronization. Phase detection means for outputting phase information indicating a phase relationship between the digital signal sequence and the first divided clock according to the frame synchronization establishment information and the input clock, and according to the phase information and the input clock The digital signal train is configured to include a second parallel conversion means for converting the digital signal train into n parallel signal trains of a predetermined array and outputting a second divided clock.

[0015]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which n digital signal trains (n is an integer of 2 or more) are used.
2 shows a case where the parallel signal sequence is converted and output.

The parallel conversion circuit 1 divides the digital signal sequence Di by n in accordance with the input digital signal sequence Di and the input clock C1 synchronized with this digital signal sequence to convert it into n parallel signal sequences, n Column signal lines 101-10
The frequency-divided clock C2 is output at the same time as it is sent to each n.

The parallel conversion circuit 2 converts the digital signal sequence Di into n parallel signal sequences according to the phase information A1 and the input clock C1 and sends them to the output signal lines 201 to 20n, respectively, and at the same time, the divided clocks. Output C3. .

The n frame synchronization circuits 11 to 1n are n
N of the parallel signal train sent to the signal lines 101 to 10n of the train
When the individual frame synchronization is established by receiving the parallel signal sequence from the n-line signal lines 101 to 10n and the divided clock C2, respectively, the frame synchronization establishment information is provided. S1
Send Sn respectively.

The phase detection circuit 3 receives the frame synchronization establishment information and the input clock C from the frame synchronization circuit in which the frame synchronization is established among the frame synchronization establishment information S1 to Sn.
1, the digital signal sequence Di and the divided clock C2
The phase information A1 indicating the phase relationship with is output.

Next, the operation will be described.

Now, for example, the frame synchronization pattern is F
, F8 digital signal train Di is converted into eight parallel signal trains, and output to the output signal lines 201 to 208 in a predetermined arrangement of F1, F2, ..., F8, respectively. And

By the way, when the parallel conversion circuit 1 converts into n parallel signal sequences, there are eight parallel signal arrays due to the phase of the frequency division lock C2. Now, as shown in FIG. 2, the parallel conversion circuits 1 to 8 output signal lines 10
Arrays sent to 1 to 108 are F4, F5, F6, F
7, F8, F1, F2, F3.

Here, the frame synchronization circuit 11 provided corresponding to each of the eight types of frame synchronization pattern arrays.
Only the frame synchronization circuits corresponding to F4, F5, ..., F3 among 18 can establish frame synchronization. For example, if only the frame synchronization circuit 14 establishes the frame synchronization, the frame synchronization circuit 14 sends the frame synchronization establishment information S4 and the other frame synchronization circuits cannot send the frame synchronization establishment information.

The phase detection circuit 3 outputs the phase information A1 indicating the phase relationship between the digital signal sequence Di and the divided clock C2 according to the frame synchronization establishment information S4 and the input clock C1.

The parallel conversion circuit 2, as shown in FIG. 3, according to the phase information A1 and the input clock C1, arranges the digital signal train Di into a predetermined array of n parallel signal trains F.
1, F2, ..., F8 and output signal lines 201-
The divided clocks C3 are output to the respective 208 and the divided clock C3 is output.

As described above, the frequency division lock of the parallel conversion circuit 1 is performed by converting the digital signal sequence Di into a parallel signal sequence of a predetermined array according to the phase information A1 generated based on the frame synchronization establishment information S4. It is not affected by the phase of C2 and always receives the input digital signal sequence Di
In contrast, the position information A1 is output with a constant delay amount, and it is possible to obtain n parallel signal sequences arranged in a predetermined array.

[0028]

As described above, according to the present invention, the phase information of the digital signal sequence and the first frequency-divided clock output from the first parallel conversion circuit is generated based on the frame synchronization establishment information. By converting the digital signal sequence into the parallel signal sequence by the second parallel conversion circuit according to the phase information, there is no influence of the phase of the first frequency division lock, and the input digital signal sequence is always present. On the other hand, it is possible to obtain n parallel signal trains that are arranged in a predetermined array with a constant delay amount.

Therefore, for example, even when the present invention is applied to digital communication in which one protection line is provided for a plurality of working lines to perform the non-instantaneous interruption synchronous switching, the non-instantaneous interruption synchronous switching can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of this embodiment.

FIG. 3 is a timing chart for explaining the operation of this embodiment.

FIG. 4 is a block diagram showing an example of a conventional frame synchronization system.

5 is a timing chart for explaining the operation of the conventional frame synchronization system shown in FIG.

[Explanation of symbols]

 1, 2 parallel conversion circuit 3 phase detection circuit 11-1n frame synchronization circuit 101-10n n-column signal line 201-20n output signal line A1 phase information C1 input clock C2, C3 frequency division clock Di digital signal sequence S1-Sn frame Synchronization establishment information

Claims (1)

[Claims] 1. A frame synchronization system for converting a digital signal sequence including a frame synchronization pattern composed of a plurality of data into n (where n is an integer of 2 or more) parallel signal sequences in frame synchronization. First parallel conversion means for dividing the column by n according to an input clock and converting it into a first parallel signal sequence of n columns, and outputting a first divided clock; and the first parallel signal sequence. Corresponding to each of the n types of frame synchronization pattern arrays, receives the first parallel signal sequence and the first frequency-divided clock, respectively, and establishes frame synchronization by the parallel signal sequence of the corresponding sequence to establish a frame. N pieces of frame synchronization means for respectively transmitting synchronization establishment information, the frame synchronization establishment information and the input clock from the frame synchronization means having established frame synchronization. Phase detecting means for outputting phase information indicating a phase relationship between the digital signal sequence and the first divided clock according to the clock, and the digital signal sequence in a predetermined arrangement according to the phase information and the input clock. And a second parallel conversion means for outputting a second frequency-divided clock while converting into n parallel signal trains.