JPH06125356A - Synchronization circuit - Google Patents

Abstract

PURPOSE:To provide a synchronization circuit able to take bit synchronization and cell frame synchronization newly for each cell. CONSTITUTION:A 1st pattern generating means 101 adds a bit synchronization pattern to each data cell and a 2nd pattern generating means 102 adds a frame synchronization pattern to each data cell. A bit phase synchronization means 103 at a receiver side starts bit phase detection operation after the reception of a cell and outputs the purport that the bit synchronization pattern of a succeeding reception cell is detected after detecting it, and a cell frame phase synchronization means 104 starts frame phase detection operation of a reception cell when the bit phase synchronization means 103 detects the bit synchronization pattern and outputs a signal representing the start of a data cell when the frame synchronization pattern is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous circuit used for cell transfer in a switch circuit portion of an ATM switch, and more particularly to a synchronous circuit suitable for a transfer system in which a guard time is provided between cells.

[0002]

2. Description of the Related Art In a conventional ATM switch having a transfer rate of several Gbit / sec or less, the switching time is sufficiently shorter than 1 bit time if a high performance element is used. Therefore, it is not necessary to provide a guard time between the cells to be transferred, and the receiving side could process the cell frame as being received periodically as shown in FIG. Therefore, the synchronization circuit only needs to perform the synchronization establishing process only when the power is turned on and when the synchronization is lost due to noise mixing, etc., and the circuit configuration may be a relatively simple one for performing the process for establishing synchronization for some cells. Met.

[0003]

However, recent optical ATs
ATM switches such as M switches have transfer rates of 10
Since it exceeds G bits / second, the switch change time cannot be ignored. That is, the accuracy of the bits before and after the switch change is not guaranteed, and it becomes necessary to provide a guard time between cells. Moreover, the guard time in the signal received on the receiving side is not constant due to a slight change in the path length due to the switch switching, and the fluctuation of the cell frame phase exceeds 1 bit.

Therefore, it is required to re-establish the bit synchronization and cell frame synchronization for each cell, but the conventional synchronizing circuit does not consider those requirements as described above. It cannot be applied to various ATM switches.

The present invention can be applied to a system such as an ATM switch in which a guard time is required between cells and the guard time is not constant due to delay variation. An object of the present invention is to provide a synchronization circuit capable of re-establishing cell frame synchronization.

[0006]

A synchronizing circuit according to the present invention is a synchronizing circuit for establishing synchronization of a received cell in a cell transfer system such as an ATM switch for transferring a cell from a transmitting side to a receiving side. The side is a guard time setting means for setting a guard time between each data cell, a bit synchronization pattern generating means for adding a bit synchronization pattern to each data cell, and a frame for adding a frame synchronization pattern to each data cell. And a bit phase synchronizing means for starting the bit phase detection operation after reception of a certain cell on the receiving side and outputting a bit synchronization pattern of the next receiving cell on the receiving side. When the phase synchronization means detects the bit synchronization pattern, it starts the frame phase detection operation of the receiving cell, and when it detects the frame synchronization pattern, the It is obtained by a frame phase synchronization means for outputting a signal indicating the start of Taseru.

[0007]

The bit phase synchronizing means and the frame phase synchronizing means in the present invention can be applied to a system in which the guard time in the received signal is not constant due to delay variation and the bit pattern appearing in the guard time is indefinite. Guarantees accurate synchronization establishment. That is, when the reception of the previous cell is completed, the bit phase synchronization means starts detection of the bit synchronization pattern included in the next reception cell, and the frame phase synchronization means, the bit phase synchronization means, detects the bit synchronization pattern. If detected, the frame synchronization pattern included in the reception cell is detected. At this time, since the bit phase synchronization means has already established the bit synchronization, the frame phase synchronization means can reliably capture the frame synchronization pattern.

[0008]

1 is a block diagram showing a basic structure of a synchronizing circuit according to the present invention, and FIG. 2 is a timing chart showing input / output data and processing timing of each block shown in FIG. . As shown in FIGS. 2A to 2D, the input data (XXXX), which is a data cell, is generated by the first pattern generating means 101 by the bit synchronization pattern (BBB).
B) is added, and the frame synchronization pattern (HIJK) is added by the second pattern generating means 102 to form a transmission cell. A certain length of guard time (GGG) is left between a certain transmission cell and the next transmission cell.

The bit pattern of the input data (XXXX) is not limited, but the bit synchronization pattern (BB)
For BB), it is more effective that there are many change points.
It is said to be an alternation of "1". Further, the frame synchronization pattern (HIJK) is easy to distinguish from the bit synchronization pattern,
Further, it is a code string such that a frame phase can be detected even if only a part is normally received on the receiving side, for example, a number string such as "1234".

The guard time in the received signal that has reached the receiving side after passing through the optical ATM switch is caused by the fact that the signals (XXXXXX, YYYYYY, ZZZZZZ) from different sources are switched by the switch. There is a case where the bit pattern is expanded and contracted as compared with the above, and the bit pattern is indefinite. Therefore, the bit phase synchronization means 103 and the cell frame phase synchronization means 104
This establishes bit phase synchronization and frame phase synchronization.

When the reception of a cell in the received signal is completed, the bit phase synchronization means 103 starts the bit phase detection operation to establish the bit phase synchronization of the next cell (FIG. 2 (f)). reference). To detect the bit phase,
It is necessary to detect a change point from "0" to "1" or from "1" to "0", and moreover, it is general to detect a plurality of change points for reliable establishment of synchronization. . When the bit phase synchronization is established, clock output is started from the bit phase synchronization means 103 and a start signal (ST1) is sent from the bit phase synchronization means 103 to the cell frame phase synchronization means 104 (FIG. 2 (g)). reference). The cell frame phase synchronization means 104 starts the frame phase detection operation in response to ST1 (see FIG. 2 (h)). Since the bit phase synchronization has already been established, the cell frame phase synchronization means 104 can reliably capture the frame synchronization pattern, and can generate the frame signal (F) at the start of data in the reception cell (FIG. 2). (See (i)).

FIG. 3 is a block diagram showing a synchronizing circuit according to an embodiment of the present invention together with an optical switch. On the transmitting side, 1 is the first pattern generating means 10 in FIG.
1 is a pattern generator for bit synchronization corresponding to 1 and 2 is shown in FIG.
The frame synchronizing pattern generating circuit corresponding to the second pattern generating means 102 in FIG. 6 is an elastic store circuit for temporarily storing the input data.

The elastic store circuit 6 takes in the input data and, as shown in FIG. 2 (a), creates each data in the form in which the cells are open for a certain time. Then, the data output from the elastic store circuit 6 is combined by the OR gate 8 with the bit synchronization pattern output from the bit synchronization pattern generation circuit 1 and the frame synchronization pattern output from the frame synchronization pattern generation circuit 2. To be done.
Here, the data read from the elastic store circuit 6, the pattern generation from the bit synchronization pattern generation circuit 1 and the frame synchronization pattern generation circuit 2, and the switching timing of the optical switch 10 are the start signal from the control circuit 7. Started at. Therefore, except for an error due to the wiring length,
The transmission signal shown in (d) is given to the electro-optical conversion circuit 9. The phase error due to the wiring length is caused by the optical switch 10
It is absorbed by the guard time together with the delay variation due to.

The electro-optical conversion circuit 9 converts the transmission signal into an optical signal and supplies it to the optical switch 10. Optical switch 10
Performs a predetermined exchange. And in the receiving circuit,
The optical-electrical conversion circuit 11 converts an optical signal into an electric signal and outputs it to the equalizing amplifier 12. The equalizing amplifier 12 performs level equalization and reproduces a digital waveform which is a received signal.

3 is a bit phase synchronizing means 10 in FIG.
3 is a bit phase synchronization circuit, which performs phase adjustment using the clock from the clock source 13 and generates an optimum reproduction clock for the phase of the change point of the bit synchronization turn. Then, it is given to the data identification circuit 14, which is a D-flip-flop, the frame phase synchronization circuit 4 and the counter 5. Also, the bit phase synchronization circuit 3
Gives a start signal (ST1) to the frame phase synchronization circuit 4 when the phase adjustment is completed. The counter 5 counts the number of clocks of the supplied clock, and when the count value reaches a value according to the number of bits of the data cell, a start signal is sent to the bit phase synchronization circuit 3 to instruct the bit phase detection for the next cell. Give (ST3).

FIG. 4 is a block diagram showing a configuration example of the bit phase synchronization circuit 3. Multi-phase clock generation circuit 30
Generates n clocks having the same period as the clock from the clock source 13 and a phase difference of T / n (T is a clock period) as shown in FIGS. (In FIG. 5, n = 6). In addition, the edge detection circuit 31
Generates a pulse having a high level section of T / n from the data change point of the received signal. Therefore, a positive pulse appears in the output of one of the n OR gates 32 corresponding to each of the n kinds of clocks, to which the clock rising immediately before or immediately after the data change point is input. In the example shown in FIG. 5, a positive pulse appears in what is input by the clocks (c) to (d) and (g) to (h).

Upon receiving the start signal (ST3), the control circuit 35 activates the selection circuit 33. The selection circuit 33 is a circuit that selects, as a reproduction clock, one that enters the OR gate 32 in which no positive pulse appears. In this case, the selection circuit 33 selects any of the clocks shown in FIGS. Which one is selected depends on the circuit design. Further, the configuration of the selection circuit 33 may be such that selection processing is performed for data change points over a plurality of bits and reliable synchronization establishment processing such as majority voting is performed. Then, when the selection circuit 33 determines the reproduction clock, it starts outputting the reproduction clock.

The pattern detection circuit 34 is a circuit for detecting a bit synchronization pattern, and detects it from the data of the received signal using the reproduction clock determined by the selection circuit 33. When the pattern detection circuit 34 detects the bit synchronization pattern, it outputs a start signal (ST1). Further, the control circuit 35 is notified of the detection. The control circuit 35 accordingly stops the operation of the selection circuit 33. .

FIG. 6 is a block diagram showing an example of the configuration of the frame phase synchronization circuit 4. The frame synchronization pattern is, for example, “10001001100” (“123” when read in 4-bit units with the head side being lower). On the receiving side, partial bit errors are allowed and "1"
If 2 "or" 23 "can be detected, the synchronization is established.

The data from the data identification circuit 14 has a length of 12 (=) driven by the clock from the bit synchronization circuit 3.
Length of pattern for frame synchronization) shift register 41
to go into. When the frame synchronization pattern arrives and the leading bit thereof reaches the final stage of the shift register 41, the outputs of the gates 42 to 44 for checking every 4 bits become high level. Then, the outputs of the AND gates 45 and 46 become high level. Further, even if there is a bit error and there is an error in the first 4 bits or the last 4 bits of the frame synchronization pattern, the output of either one of the AND gates 45 and 46 becomes high level. AND gate 45, 45 of 46,
When at least one of the outputs of 46 goes high, the output of the OR gate 47 goes high. Since the RS flip-flop 48 is set by the start signal (ST1) from the bit synchronization circuit 3, the output of the AND gate 49 becomes high level, and as a result, the start signal (ST1).
When the frame synchronization pattern is first detected after receiving the signal, the output of the D flip-flop 50 becomes high level.

In this way, the D flip-flop 50
Outputs a frame signal output (F) (FIG. 2 (i)).
reference). Since the RS flip-flop 48 is reset by the frame signal output, even if the same bit string as the frame synchronization pattern appears in the cell by accident, the frame signal output is not output at that time. Also,
The counter 5 is triggered by the input of a start signal (ST3) that is output at the same time as the frame signal output, and the bit synchronization circuit 3
The clocks from 1 to 3 are counted, and the start signal (ST1) is output when the count value becomes equal to the bit length of the cell data. Then, the bit synchronization circuit 3 restarts detection of the bit synchronization pattern for the next cell reception.

[0022]

As described above, according to the present invention, A
The synchronization circuit used for the TM switch or the like starts the bit phase detection for the next cell reception after the cell reception is completed, and starts the frame phase detection when the bit synchronization is established. Is required, and when the guard time length fluctuates on the receiving side or the bit pattern in the guard time is undefined,
There is an effect that it is possible to provide a reception cell that can be reliably synchronized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a synchronizing circuit according to the present invention.

FIG. 2 is a timing chart showing input / output data and processing timing.

FIG. 3 is a block diagram showing a synchronization circuit according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a bit phase synchronization circuit.

FIG. 5 is a timing diagram showing an example of a multiphase clock.

FIG. 6 is a block diagram showing a configuration example of a frame phase synchronization circuit.

FIG. 7 is an explanatory diagram showing an example of a conventional received signal format.

[Explanation of symbols]

 1-bit synchronization pattern generation circuit 2 Frame-synchronization pattern generation circuit 3-bit phase synchronization circuit 4 Frame phase synchronization circuit 5 Counter 6 Elastec store circuit 7 Control circuit 9 Electric-optical conversion circuit 10 Optical switch 11 Optical-electric conversion circuit 13 Clock source 30 Multi-phase clock generation circuit 31 Change point detection circuit 33 Selection circuit 34 Pattern detection circuit 35 Control circuit 101 First pattern generation means 102 Second pattern generation means 103 Bit phase synchronization means 104 Cell frame synchronization means 105 Counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ouyoshi Yamazaki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. A synchronizing circuit for establishing synchronization of a received cell in a system for transferring a cell from a transmitting side to a receiving side, guard time setting means for setting a guard time between data cells on the transmitting side, A bit synchronization pattern generation means for adding a bit synchronization pattern to each data cell, and a frame synchronization pattern generation means for adding a frame synchronization pattern to each data cell are provided. A bit phase synchronization unit that starts the bit phase detection operation and outputs a signal indicating that the bit synchronization pattern of the next reception cell is detected, and a frame phase detection of the reception cell when the bit phase synchronization unit detects the bit synchronization pattern When the operation is started and the pattern for frame synchronization is detected, a signal indicating the start of the data cell is output. Synchronizing circuit comprising the and.