JPH10308082A - Data separator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data separator capable of realizing highly reliable operation with a comparatively simple circuit configuration. SOLUTION: A digital circuitry is composed of a rising edge detecting circuit 1, a synchronization starting circuit 2, a phase synchronizing circuit 3 and a separator circuit 4. The circuit 1 detects the rising edge of modified frequency modulation(MFM) data using a clock signal C. The circuit 2 accepts the clock signal C, a synchronization enable signal ESYNC, a data edge pulse signal DE to output a clock region detecting signal SG when the MFM data DM is in the clock region. The circuit 3 accepts the signals C, ESYNC, DE and SG to generate a data window signal DW which becomes 'H' when the data edge pulse signal DE holds the original data. The circuit 4 outputs separated data or a clock when the data window signal DW is 'H' or 'L' and in addition the data edge pulse signal DE is 'H'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data separator having a digital circuit structure and used as an interface of an auxiliary storage device in a computer system.

[0002]

2. Description of the Related Art When data transfer between a computer and an auxiliary storage device is a serial transfer, MFM is used for encoding.
(Modified frequency modul
ation) method may be used.

[0003] The MFM code is obtained by adding a clock for synchronizing serial data, as shown in FIG. The rules for MFM encoding are as follows.

(1) When data is present (when "1"), a data bit D is output at the center of the cell. (2) If there is no data (when "0"), clock C is output at the head of the current cell when there is no data bit in the immediately preceding cell. When decoding MFM data to original data, use MFM
Separate data into data and clock. In that case, MF
The M data always has a clock region only for a clock in order to synchronize with the separator circuit. First, synchronization is performed in the clock region, and then data and clock are separated in the data region following the clock region.

[0005]

The separator circuit for decoding the MFM data into the original data is generally composed of a very complicated analog circuit. The degree of influence of the characteristics is high, and there is a problem in the operation reliability of data decoding.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data separator which can be expected to have high operation reliability while having a relatively simple circuit configuration by using a digital circuit. .

[0007]

According to the present invention, there is provided a rising edge detecting circuit for detecting a rising edge of an MFM data signal and outputting a data edge pulse signal which becomes "H" with a pulse width of one clock of a clock signal; When the synchronizing enable signal (“H” level when synchronizing with the clock signal and starting the operation of separating data and clock) is “H”, a continuous clock area of the MFM data signal, that is, the data edge pulse signal Receiving a clock signal, a synchronization enable signal, and a clock area detection signal; a synchronization start circuit that outputs a clock area detection signal that becomes “H” when a signal having a reciprocal cycle of the transfer rate of the MFM data signal in the above is repeated the required number of times. Synchronize with the data edge pulse signal based on the clock signal, and A phase synchronization circuit that outputs a data window signal (which becomes "H" when the data edge pulse signal is the original data) for separating the clock signal, a clock signal, a synchronization enable signal, a clock area detection signal, and a data window signal. When the data window signal is "H" and the data edge pulse signal becomes "H", "data (H" level) is output to the data (DATA) terminal and the data window signal is "L". A separator circuit for outputting a clock (“H” level) to a clock (CLOCK) terminal when the data edge pulse signal sometimes becomes “H”, and each circuit is constituted by a digital circuit.

In this case, the frequency of the clock signal is set to eight times the data transfer rate of the MFM data signal so that the jitter of one cycle before and after the reference clock can be ignored in the data area.

[0009]

FIG. 1 shows an embodiment of the present invention. In the figure, 1 is a rising edge detection circuit, 2 is a synchronization start circuit, 3 is a phase synchronization circuit, 4 is a separator circuit, and each of the circuits 1 to 4 has a digital circuit configuration. The rising edge detection circuit 1 detects a rising edge of the MFM data signal D _M and outputs a data edge pulse signal D _E which becomes “H” with a pulse width of one clock of the clock signal C. For example, the MFM data signal D _M is latched by the clock signal C to prevent metastable,
When a rising edge of the data signal D _M is detected, an “H” output is generated. The clock signal C, MFM data signal D _M of the data transfer rate of 8 times the frequency (e.g., when the transfer rate of the MFM data signal D _M is 5 Mbps, 40MH
z). The clock signal C is supplied to the synchronization start circuit 2,
It is also input to the phase synchronization circuit 3 and the separator circuit 4. Similarly, the data edge pulse signal _DE is also supplied to the synchronization start circuit 2,
The signals are input to the phase synchronization circuit 3 and the separator circuit 4.

The synchronization start circuit 2 has a synchronization enable signal E
When _SYNC is "H", a continuous clock domain of the MFM data signal D _M, i.e., when the signal of the period of the reciprocal of the transfer rate of the MFM data signal D _M in the data edge pulse signal D _E is continuous 64 times "H" Is output. The synchronization enable signal _ESYNC becomes "H" when synchronizing with the clock signal C and starting the operation of separating data and clock. The synchronization enable signal E _SYNC is also input to the phase synchronization circuit 3.

The phase synchronization circuit 3 has a synchronization enable signal E
_SYNC and the clock area detection signal SG, and synchronizes with the data edge pulse signal _DE based on the clock signal C,
Data window (DATAWINDOW) for separating data edge pulse signal _DE into data and clock
The signal DW is output. The data window signal DW is “H” when the data edge pulse signal _DE is the original data.
Becomes This is input to the separator circuit 4.

The separator circuit 4 outputs "data D (H) level" to a data (DATA) terminal when the data edge pulse signal _DE becomes "H" when the data window signal DW is "H". If the data edge pulse signal _DE goes high while the data window signal DW is low, a clock C ("H" level) is output to the clock (CLOCK) terminal.

FIGS. 2 and 3 show specific timing charts. FIG. 3 is an enlarged view of the section α in FIG. The clock signal C and the MFM data signal D _M are continuously input to the rising edge detection circuit 1. sync enable signal E _SYNC for permitting the operation of the data separator t ₁ point to "H". Thereafter, at time t ₂ , the MFM data signal D _M becomes a clock region, and the synchronization start circuit 2 counts the number of times the data edge pulse signal D _E becomes “H” at regular intervals. Once counted consecutively 64 times with t ₃ time, the clock area detection signal SG becomes "H". Thus, it can be seen that the clock pulse is continuously “H” in the data edge pulse signal _DE . Therefore, in the phase synchronization circuit 3,
The data window signal DW is generated in synchronization with the data edge pulse signal _DE . Thereafter, since the clock area until just before t ₄ time, the CLOCK terminal "H"
Level output continues.

[0014] becomes MFM data signal D _M is the data area from t ₄ time, the signal clock is added to the data. data bits MFM data signal D _M is input at t ₄ time. At this time, since the data window signal DW is "H", the data edge pulse signal _DE indicates a data bit. Therefore, the separator circuit 4
Sets the data signal at the DATA terminal to "H". Also,
clock bits are input to the MFM data signal D _M at t ₅ the time. At this time, since the data window signal DW is "L", the data edge pulse signal _DE indicates a clock bit. Therefore, the separator circuit 4 sets the clock signal of the CLOCK terminal to “H”.

[0015] Thereafter, until the next synchronization enable signal E _SYNC goes "L" to "H", by using the data window signal DW with synchronized to t ₃ point continues to separate the data and clock.

[0016]

As described above, according to the present invention, a rising edge detection circuit, a synchronization start circuit,
Since the MFM data decoding circuit is configured by the phase synchronization circuit, the separator circuit, and the like, variations in characteristics of circuit components are reduced, and operation reliability can be improved.
Further, since each circuit is configured by a flip-flop, a counter, or the like, it can be realized with a relatively simple circuit configuration. Furthermore,
Since the frequency of the reference clock for synchronizing is set to eight times the data transfer rate of the MFM data signal, even if jitter (phase shift) occurs in the MFM data signal for one period before and after the reference clock, the data is not affected. There is an advantage that it operates without problems in the area.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is an enlarged view of a section α in FIG. 2;

FIG. 4 is an explanatory diagram of an MFM code used in data transfer between a computer and an auxiliary storage device.

[Explanation of symbols]

1 ... Rising edge detection circuit 2 ... sync start circuit 3 ... phase synchronization circuit 4 ... separator circuit C ... clock signal D _M ... MFM data signal D _E ... data edge pulse signal E _SYNC ... synchronization enable signal SG ... clock area detection signal DW ... Data window signal DATA ... Data CLOCK ... Clock

Claims (2)

[Claims] 1. A rising edge of an MFM data signal is detected, and “H” is output with a pulse width of one clock of a clock signal.
A rising edge detection circuit that outputs a data edge pulse signal, and a synchronization enable signal (“H” level when synchronizing with the clock signal and starting the operation of separating data and clock) is “H” , MFM in the continuous clock region of the data signal, ie, the MF in the data edge pulse signal.
A synchronization start circuit for outputting a clock region detection signal which becomes “H” when a signal having a cycle of a reciprocal of the transfer rate of the M data signal is repeated for a required number of times; a clock signal, a synchronization enable signal and a clock region detection signal; Synchronize with the data edge pulse signal based on the signal, and output a data window signal for separating the data edge pulse signal into data and clock ("H" when the data edge pulse signal is the original data). Receiving a clock signal, a synchronization enable signal, a clock area detection signal, and a data window signal; and when the data window signal is "H", the data edge pulse signal is "H".
When the data window signal is "L", the data (DATA) terminal outputs "data (H) level". When the data window pulse signal is "L" and the data edge pulse signal becomes "H", the clock (CLOCK) terminal is output. Clock (“H”)
A data separator comprising a separator circuit for outputting a level signal and a digital circuit for each circuit. 2. The data separator according to claim 1, wherein the frequency of the clock signal is eight times the data transfer rate of the MFM data signal.