JPS6350896B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a staff synchronization circuit, and particularly to a staff synchronization circuit for a wireless line.

Conventionally, this type of staff synchronization circuit for wireless lines includes many similar components, but the transmitting side circuit and the receiving side circuit are designed and manufactured separately.In this case, the development cost and prototyping cost are low. The drawback was that it was nearly twice as expensive.

The present invention uses a phase comparator that can be shared by the transmitting side and the receiving side in the staff synchronization circuit, and includes a switch inside so that the functions of the transmitting side and the receiving side can be realized separately. The present invention provides a circuit that can realize both transmitting and receiving functions.

According to the present invention, there is an input terminal for receiving an input signal, an elastic memory connected to the input terminal for storing the input signal, and a reception signal output for outputting the output from the elastic memory to the outside as a reception output signal. a multiplexing circuit for receiving the output of the elastic memory; a transmission signal output means for outputting the output of the multiplexing circuit to the outside as a transmission output signal; and a first clock for receiving a first clock synchronized with the input signal. a second clock input terminal for receiving a second clock; and means for applying the second clock to the receive signal and transmit signal output means for timing the receive and transmit output signals. , said second
a frame timing generator for generating timing signals for at least a frame synchronization signal and a staff information signal; and a frame timing generator for generating timing signals for at least a frame sync signal and a staff information signal; means for multiplexing the synchronization signal and the staff information signal; a first switch for selecting the first clock or the second clock as the clock for operating the frame timing generator; and removal of the clock for staff synchronization. a second switch for selecting whether to operate on the first clock or the second clock; a first gate for removing the first clock in response to the output of the second switch; a second gate for removing the second clock in response to another output of the second switch; and dividing the output of the first gate to provide first and second divided outputs; a first frequency divider that drives an elastic memory with a frequency divided output of , and a second frequency divider that divides the output of a second gate to produce third and fourth frequency divided outputs; A second frequency divider for driving the elastic memory, a phase comparator for comparing the phases of the second and fourth frequency division outputs, and staff information for reading out the staff information multiplexed in the input signal. A staff comprising a readout circuit and a third switch for selecting whether to use a signal according to the output of the phase comparator or a signal according to the output of the staff information readout circuit as an input signal of the second switch. Obtain a synchronous circuit.

Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, the embodiment of the present invention shows a staff synchronization circuit for a wireless line that is used for both transmission and reception, and includes a data input terminal 10, a first clock input terminal 11 synchronized with the data, and an output data terminal 10. a second clock input terminal 20 for reading data, an output terminal 30 for data before multiplexing, an output terminal 31 for data after multiplexing, an output terminal 32 for a clock synchronized with the data, and an input terminal for frame pulses. Terminal 40 and output terminal 5 of the phase comparator
0, the first clock 101 from the clock input terminal 11 and the first clock inhibit pulse 1
02 as an input, a first frequency divider 104 that operates with the output of the gate 103, and a second clock 201 and a second clock input from the clock input terminal 20. a second clock inhibit gate 203 which receives the inhibit pulse 202;
a second frequency divider 204 that operates with the output of the frequency divider 204, a phase comparator 210 that compares the phases of the frequency divider 104 and the frequency divider 204, a flip-flop 211 for holding the output, and the frequency divider 104. Elastic memory 300 controlled by the output of frequency divider 204
, a frame timing generator 400, a staff information readout circuit 500 that reads out staff information from input data, a multiplexing circuit 310 that multiplexes a frame synchronization signal, staff information, etc. into the elastic memory output. A flip-flop 330 that reads the multiplexing circuit input signal and outputs it to the data output terminal 30, and a multiplexing circuit 310.
A flip-flop 331 outputs the read output signal to the data output terminal 31, an inhibit pulse generator 450 is controlled by the output of the frame timing generator 400, and a clock input terminal 20 receives the signal from the clock input terminal 20 on the transmitting side. a first switch 601 that selects the signal at the input terminal 11 and supplies it to the frame timing generator 400;
The output clock inhibit pulse 451 of the clock inhibit pulse generator 450 is sent to the gate 203 on the transmitting side and to the gate 103 on the receiving side.
On the transmitting side, the signal 405 that controls the timing of the second switch 602 and the stuff pulse of the clock inhibit pulse generator 400 is used as the output signal 212 of the flip-flop 211 that holds the output of the phase comparator 210 within one frame. , and a third switch 603 that outputs the output signal 501 of the staff information reading circuit 500 on the receiving side.

FIG. 2 shows the timing relationship among the frame pulse 401, frame synchronization pulse timing signal 402, staff information pulse timing signal 403, and staff pulse timing signal 404, which are the output signals of the frame timing generator 400. , an example is shown in which frame synchronization pulses, staff information pulses, and staff pulses are sequentially multiplexed periodically every N bits in transmitting side output data or receiving side input data.

FIG. 3 shows the configuration and operation of the phase comparator 210. For two input signals, input 1 and input 2, shown in b, the output of the phase comparator 210 is shown in c.
As shown in the figure, the waveform becomes a rectangular wave corresponding to the phase difference φ.

FIG. 4 shows the configuration of a sending-side staff synchronization circuit using the circuit of the present invention shown in FIG. 1. The data input terminal 10,
A data clock to be synchronized is connected to the clock input terminal 11, and this data is input to the main clock generator 60, which is input to the second clock input terminal 20.
The staff will be synchronized.

Staff synchronization is the synchronization of a plurality of originally asynchronous signals to one main clock, and in the explanation of this embodiment, for convenience, the operation of synchronizing a single signal on the transmitting side and the receiving side will be shown. Of course, the embodiments of the present invention can be configured in exactly the same way even when a plurality of asynchronous signals are handled.

The operation on the sending side is as follows. The frame timing generator 400 is operated by a second clock, that is, the main clock generator 60, and as a result of phase comparison between the first clock and the second clock, it is determined that the second clock has a higher frequency than the first clock. When the clock phase advances beyond a certain value, it is judged once per frame at the timing of the frame pulse, and once per frame at the timing of the stuff pulse, the second clock is deleted once, the phase is delayed, and the frequency is divided. 204. In the multiplexing circuit 310, frame synchronization signal staff information, staff pulses, etc. are multiplexed. The outputs of the data output terminal 31 and the clock output terminal 32 become transmission signals.

FIG. 5 shows the configuration of a receiving side staff synchronization circuit using the circuit of the present invention shown in FIG. The output of the voltage controlled oscillator 70 which uses the output of the phase comparator output signal terminal 50 as an automatic phase control signal is connected to the second clock input terminal 20, and the outputs of the data output terminal 30 and the clock output terminal 32 are received. It is used as the side output signal. The frame timing generator 400 on the receiving side is reset by the synchronization pulse from the frame synchronization circuit 80 placed before this circuit, and operates using the signal at the first clock input terminal 11 as a clock. The inhibit pulse generator 450 determines whether or not stuffing has been performed on the transmitting side based on the output of the staff information readout circuit 500 that reads out the stuff information multiplexed in the transmitting side circuit. A clock inhibit pulse 501 is output at the timing of the pulse. This clock inhibit pulse 50
1 is input to the clock inhibit gate 103 through the second switch 602, and inhibits the reception demodulation clock, that is, the first clock, only at the timing of the pulse added on the transmitting side.
The first signal that was inhibited at this specific timing
The voltage controlled oscillator 70 is controlled by the result of phase comparison between the first clock pulse and the second clock pulse, and if observed over a long period of several frames, the number of rises of both clocks is controlled to be equal.

In this way, by using the circuit of the present invention,
A single type of circuit can configure the staff synchronization circuits on the transmitting side and the receiving side.

As explained above, the present invention has a wireless line staff synchronization circuit configured so that one circuit can be used for both the transmitting side and the receiving side.
By manufacturing different types of circuits, the transmitting and receiving functions can be achieved. Compared to manufacturing two types of circuits, the cost of designing and prototyping can be nearly halved, and the production volume per circuit can be doubled. As a result, cost reductions can be expected as people become more proficient.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a block diagram of a staff synchronization circuit for a wireless line used for transmission and reception, which is an embodiment of the present invention, and FIG. 2 is an output of the frame timing generator shown in FIG. 1. FIGS. 3a to 3c are explanatory diagrams showing the configuration and operation of the phase comparator, respectively. FIG. 4 is a timing diagram showing an example of a signal, and FIG. FIG. 5 is a block diagram showing a receiving side staff synchronization circuit using the circuit of the present invention shown in FIG. 2. In the figure, 10...data input terminal;
11...First clock input terminal, 20...Second clock input terminal
clock input terminal, 30... data output terminal before multiplexing, 31... data output terminal after multiplexing,
32... Clock output terminal, 40... Frame pulse input terminal, 50... Phase comparator output terminal, 60... Main clock oscillator, 70... Voltage controlled oscillator, 80... Frame synchronization circuit, 101...
...first clock, 102...first clock inhibit pulse, 103...first clock inhibit gate, 104...first frequency divider, 2
01...Second clock, 202...Second clock inhibit pulse, 203...Second clock inhibit gate, 204...Second frequency divider, 210...Phase comparator, 211 ...flipflop, 300...elastic memory,
400...Frame timing generator, 500...
...staff information read circuit, 310... multiplexing circuit, 330... flip-flop, 331... flip-flop, 450... inhibit pulse generator, 601... first switch, 602...
A second switch 603...a third switch.

Claims (1)

[Claims] 1: an input terminal for receiving an input signal; an elastic memory connected to the input terminal for storing the input signal; a received signal output means for outputting an output from the elastic memory to the outside as a received output signal; a multiplexing circuit that receives the output of the elastic memory; a transmission signal output means that outputs the output of the multiplexing circuit to the outside as a transmission output signal; and a first clock input that receives a first clock synchronized with the input signal. a second clock input terminal for receiving a second clock; means for providing the second clock to the receive signal and transmit signal output means for timing the receive and transmit output signals; a frame timing generator that generates timing signals for at least a frame synchronization signal and a staff information signal; means for multiplexing the frame synchronization signal and the staff information signal, and a first switch for selecting the first clock or the second clock as a clock for operating the frame timing generator, for performing staff synchronization; a second switch for selecting whether to remove the first clock or the second clock;
a first gate that removes the second clock depending on the output of the second switch; a second gate that removes the second clock depending on the other output of the second switch; and a second gate that separates the output of the first gate. a first frequency divider that divides the output of the second gate to produce first and second divided outputs and drives the elastic memory with the first divided output; comparing the phases of the second and fourth divided outputs with a second frequency divider that produces third and fourth divided outputs and drives the elastic memory with the third divided outputs; A phase comparator, a staff information reading circuit for reading out the staff information multiplexed in the input signal, and a signal corresponding to the output of the phase comparator as the input signal of the second switch. or a third switch for selecting whether to use a signal corresponding to the output of the staff information reading circuit.