JP2594765B2 - Time division multiplex circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multiplexing circuit for performing stuff synchronous multiplexing of input digital data synchronized with an input clock and additional information such as an alarm signal in synchronization with a multiplexed clock. The present invention relates to a time-division multiplexing circuit suitable for digital microwave communication devices and the like that time-division multiplexes additional information such as a frame signal and an alarm signal to audio data and the like in various PCM hierarchies.

[0002]

2. Description of the Related Art An example of a conventional time-division multiplexing circuit is disclosed in Japanese Patent Laid-Open Publication No. 1-149544 (title of the invention: stuff synchronous communication system) (particularly, FIGS. 2 and 4 and FIG. Figure). This time division multiplexing circuit
The input digital data (frame data in the publication) is speed-converted to the speed of the multiplexed clock by stuff synchronization control, and additional information (sub-signal in the publication) is inserted at the stuff insertion position to transmit the additional information without lowering the transmission efficiency. Multiplexed to input digital data.

[0003]

In the above-described conventional time-division multiplexing circuit, the speed of the multiplexed data after the speed conversion is limited by the condition of the stuff synchronization. For this reason,
In the conventional time division multiplexing circuit, if the PCM hierarchy of the microwave communication device or the like cannot be realized by one stuff synchronization control, the stuff synchronization control is performed twice or three times to increase the speed of the multiplexed data. It was necessary to set the speed of the PCM hierarchy. If such stuff synchronization control is performed a plurality of times, not only does the circuit scale increase, but also stuff jitter is added.

As an example, 64 kb / s digital audio data is converted to 100 bits using a conventional time-division multiplexing circuit.
To multiplex to kb / s microwave channel multiplexed data, the speed of the multiplexed data is first converted to about 72 kb / s, which is within the conditions for stuff synchronization, and then 100 kb again.
/ S.

[0005]

SUMMARY OF THE INVENTION A time division multiplexing circuit according to the present invention responds to input digital data in response to 8-bit input digital data, an input clock synchronized with the input digital data, and a multiplexed clock. It is composed of digital data, frame bits of a first frame pattern synchronized with the most significant bit of the digital data, and stuff bits inserted every M (M is an integer of 2 to 16) bits. First multiplexing means for generating intermediate digital data having a frame bit interval of a first frame at the speed of the multiplexing clock, and adding additional information bits and frame bits of a second frame pattern to the stuff bits of the intermediate digital data. Alternately inserted at the position of the second frame according to the second frame pattern. And a second multiplexing means to produce a multiplexed data structure to a double frame construction.

One of the time-division multiplexing circuits is a temporary storage circuit in which the first multiplexing means temporarily stores the input digital data so that the position of the most significant bit can be determined; A first frame pattern generator for generating the first frame pattern in response to the first frame pattern; and a multiplexing control signal having the first frame as a cycle in response to the input clock reference signal and the multiplexed clock reference signal. A multiplexing control signal generating unit that is generated at a position of a time slot immediately before the most significant bit of the digital data in the intermediate digital data, and the input digital data stored in the temporary storage circuit in synchronization with the multiplexing control signal. The multiplexed control signal is read while the stuff bit is inserted and the frame bit of the first frame pattern is read. Can be inserted into position a configuration comprising a first multiplexing circuit producing said intermediate digital data.

The time division multiplexing circuit includes: a second frame pattern generator, wherein the second multiplexing means generates a frame bit of the second frame pattern every 2M clocks in response to the multiplexed clock; A timing signal generator that generates a timing signal at the position of the stuff bit in response to the multiplexed clock; and the additional information bit and the frame bit of the second frame pattern are alternately arranged at the position of the stuff bit by the timing signal. Multiplexed with the intermediate digital data and multiplexed with the intermediate digital data to generate the multiplexed data.

Another one of the time-division multiplexing circuits is characterized in that the frame bits of the first frame pattern are generated at every nine clocks of the missing clock obtained by removing the multiplexed clock every M clocks. , The multiplexed data may be arranged in a time slot immediately before the most significant bit of the input digital data.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a time division multiplexing circuit according to the present invention. FIG. 2 is a timing chart of main signals in this embodiment. FIG. 3 is a timing chart of signals input to and output from the timing generator 4 of the present embodiment.

Referring to FIGS. 1, 2 and 3 together,
This time division multiplexing circuit is provided on the transmitting side of a digital microwave communication device or the like. The time division multiplexing circuit converts an analog audio signal into an 8-bit digital data D from an A / D conversion circuit (not shown) or the like (not shown).
And a clock C synchronized therewith and a sampling clock S obtained by sampling the clock C every eight clocks in synchronization with the most significant bit (hereinafter, MSB) of the digital data D
P, and receives additional information (additional information bit) A such as an alarm signal from a monitoring circuit or the like (not shown). The time-division multiplexing circuit has multiplexed data B output from its own circuit.
And a multiplexing device for multiplexing a plurality of digital data similar to the above, receives a multiplexed clock E faster than the clock C.

The first multiplexing circuit of the time division multiplexing circuit includes a temporary storage circuit 1, a phase comparator 2, a stuff control circuit 3, a first frame pattern generator 5, a first multiplexing circuit 6, and a timing generation circuit. A multiplexing control signal S3 for synchronizing a digital data D and a frame bit of a first frame pattern S5 generated by a first frame pattern generator 5 with a multiplexing clock E, using a multiplexing control signal S3. 6
To multiplex. The intermediate digital data S6 from the first multiplexing circuit 6 is obtained by stuff synchronous multiplexing of 8-bit digital data D and frame bits of the first frame pattern S5. Synchronized with. Further, stuff bits are inserted into the intermediate digital data S6 substantially every M bits. The frame bit interval of the first frame pattern is referred to as a frame period of the first frame.

The second multiplexing circuit of the time division multiplexing circuit comprises a second frame pattern generator 7, a second multiplexing circuit 8, and a timing generator 4. Second multiplex circuit 8
Is the intermediate period of the generation cycle of the timing signal S4d from the timing generator 4, that is, the additional information bit A and the frame bit of the second frame pattern S7 from the second pattern generator 7 every M clocks of the multiplexed clock E. The data S6 is inserted alternately for every M bits. The multiplexed data B, which is the output data of the second multiplexing circuit 8, uses the 2M clock cycle of the multiplexed clock E (two cycles of the timing signal S4d) as the frame cycle in addition to the first frame. This frame is called a second frame. Therefore, the multiplexed data B has a double frame configuration.
The multiplexed data B is sent to a receiving device paired with the transmitting device after being subjected to an operation such as modulation.

Here, each signal shown in FIGS. 2 and 3 will be described. The digital data D is, for example, digital data such as audio data at a data rate of 64 kb / s, and is input to the temporary storage circuit 1 in 8-bit units.
The multiplexing clock E is a multiplexing clock of the PCM hierarchy, and is selected from about 76 kb / s to 102 kb / s when the digital data D is 64 kb / s. In FIGS. 2 and 3, the first bit is set every 8 bits of the digital data D.
This indicates that one frame bit of the frame pattern S5 is added. Note that the frame period 2M of the second frame is 22.

Hereinafter, the time division multiplexing circuit will be described in more detail.

In this time division multiplexing circuit, the temporary storage circuit 1
Temporarily stores the digital data D in units of 8 bits.
Since the frame period of the frame is set to 2M bits, the timing signal 4
a, S4b, S4c and S4c are generated in response to the multiplexed clock E. The timing signal S4d includes an additional information bit A and a second signal every frame period of the second frame.
This is a timing signal for reading one bit of the frame pattern S7 into the second multiplexing circuit 8, and is a multiplexing clock E
M = 11 pulses every clock. The timing signal S4c is a timing signal for the second frame pattern generator 7, and is a signal synchronized with the timing signal S4d every 22 multiplexed clocks E.
The timing signal S4a is the clock C (or the clock C
This is the reference of the multiplexed clock E for comparing the phase with the sampling clock SP synchronized with the multiplexed clock E. The timing signal S4a is generated by removing the missing clock obtained by removing the multiplexed clock E every M = 11 clocks and further removing the missing clock every 9 clocks. The timing signal S4b is a timing signal for the first frame pattern generator 5, and is a signal having one cycle of eight clocks of the timing signal S4a.

Temporary storage circuit 1 of the first multiplexing circuit section
Responds to the digital data D, the clock C, and the sampling clock SP, and outputs the serial digital data D
Is temporarily stored in a parallel format in each of the built-in flip-flops (hereinafter referred to as F / F) 11 to 18 so that the MSB can be determined in 8-bit units. That is, the F / F 11 stores the MSB of the digital data D, and the F / F 18 stores the least significant bit (LSB) in the code order of the F / F in correspondence with the input order of the digital data D. Each F /
As a write clock to the C terminal of F, a clock obtained by dividing the clock C by 8 by the frequency divider 10 is used. In addition,
The digital data D stored in the temporary storage circuit 1 is read out to the first multiplexing circuit 6 as digital data S1 from the Q terminal of each F / F by the multiplexing control signal S3 as described later.

The phase comparator 2 and the stuff control circuit 3
A stuff control signal generation unit is configured to compare the signal phase based on the clock C with the signal phase based on the multiplexed clock E and generate a stuff control signal S2 for specifying stuff control. The phase comparator 2 compares the phase of the sampling clock SP with the multiplexed control signal S3, which is a divide-by-8 signal of the stuff-controlled signal by the stuff control circuit 3, and generates a stuff control signal S2 indicating the phase difference. Output.
The stuff control circuit 3 receives the stuff control signal S2,
The phase of the multiplex control signal S3 is the sampling clock SP
When the phase approaches a predetermined value, the pulse interval of the multiplexing control signal S3 is extended by one clock of the multiplexing clock E to perform the stuff synchronization control. FIG. 2 does not show the state of the stuff synchronization control performed at an undefined time.

The first frame pattern generator 5 outputs the first frame pattern S every one cycle of the timing signal S4b.
Yields 5 one frame bits. The first frame pattern S5 is a pattern composed of, for example, 8 bits “00011101”.

The first multiplexing circuit 6 synchronizes each bit of the parallel digital data S1 stored in the temporary storage circuit 1 with one frame bit of the first frame pattern S5 in synchronization with the multiplexing control signal S3. The data is read out and stuff-synchronous-multiplexed to generate serial digital data S6. The signal interval of the multiplex control signal S3 is substantially equal to the frame period of the first frame, and the first multiplex circuit 6 inserts the frame bits of the first frame pattern at the position of the multiplex control signal S3. Therefore, this frame bit is located in the time slot immediately before the MSB of the intermediate digital data S6 corresponding to the digital data D. It should be noted that one stuff bit is generated in the intermediate digital data S6 every M clocks of the multiplexed clock E.

The second frame pattern generator 7 of the second multiplexing circuit receives the timing signal S4c and generates a frame bit of the second frame pattern S7 every 2M clocks of the multiplexed clock E. As the second frame pattern S5, a pattern consisting of 8 bits can be used.

The second multiplexing circuit 8 has a timing signal S4d.
Information bit A and the second frame pattern S
7 are alternately inserted at the positions of the stuff bits of the intermediate digital data S6, and are multiplexed with the intermediate digital data S6, the additional information bits A, and the second frame pattern S7. 2
The multiplexed data B having the frame period of the frame is generated.

As described above, the time-division multiplexing circuit of the present embodiment multiplexes the additional information bits A and digital data D at the speed of the multiplexing clock E to form the first frame before the second frame. The first frame is further configured by inserting the frame bits of the pattern S5 in synchronization with the MSB of the digital data D in units of 8 bits, and receives a signal corresponding to the multiplexed data B having the double frame configuration. It is sent to the device side.

As a result, this time-division multiplexing circuit is 64k
Even when digital audio data of b / s is multiplexed into multiplexed data for microwave links having a high speed of 100 kb / s, the stuff synchronization control and the speed conversion are performed by one.
Therefore, not only the circuit size can be reduced, but also the addition of stuff jitter can be eliminated.

[0025]

As described above, according to the present invention, the digital data corresponding to the input digital data in response to the input digital data in units of 8 bits, the input clock synchronized with the input digital data and the multiplexed clock, and Intermediate digital data composed of a frame bit of a first frame pattern synchronized with the most significant bit of the digital data and a stuff bit inserted every M bits and having a frame bit interval of the first frame pattern as a first frame. The first multiplexing means generated at the speed of the multiplexing clock, and the additional information bits and the frame bits of the second frame pattern are alternately inserted at the positions of the stuff bits of the intermediate digital data to form the second frame pattern. Multiplexed data in a double frame configuration in which the second frame is also configured by When the low-speed digital data is multiplexed with the high-speed digital data, the speed can be converted by one stuff synchronization, and the circuit scale can be reduced. There is an effect that addition of jitter can be eliminated.

Further, even if the signal corresponding to the multiplexed data passes through a noisy line such as a radio line, the receiving apparatus will immediately transmit the MSB of the input digital data contained in the multiplexed data. Since it is known that the frame bits of the first frame are multiplexed, there is an effect that frame communication can be easily performed and stable communication transmission with little stuff jitter can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a time division multiplexing circuit according to the present invention.

FIG. 2 is a timing chart of main signals in the embodiment.

FIG. 3 is a timing chart of signals input to and output from the timing generator 4 of the present embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Temporary memory circuit 2 Phase comparator 3 Stuff control circuit 4 Timing generator 5 First frame pattern generator 6 First multiplex circuit 7 Second frame pattern generator 8 Second multiplex circuit 10 Divider circuit 11-18 Flip-flop (F / F)

Claims (5)

(57) [Claims] 1. In response to input digital data in units of 8 bits, an input clock synchronized with the input digital data, and a multiplexed clock, the digital data corresponding to the input digital data and the most significant bit of the digital data are synchronized. Frame bits of the first frame pattern and M
(M is an integer of 2 to 16) and a stuff bit inserted every bit, and intermediate digital data having a frame bit interval of the first frame pattern as a first frame is generated at the speed of the multiplexing clock. A multiplexing means, wherein a second frame is also constituted by the second frame pattern by alternately inserting additional information bits and frame bits of a second frame pattern at the positions of the stuff bits of the intermediate digital data. A second multiplexing means for generating multiplexed data having a frame configuration. 2. A temporary storage circuit for temporarily storing the input digital data so that the position of the most significant bit of the input digital data can be determined, and the first frame responsive to the multiplexing clock. A first frame pattern generator for generating a pattern; and a multiplexing control signal having a cycle of the first frame in response to the input clock reference signal and the multiplexed clock reference signal. And a multiplexing control signal generation unit generated at the position of the time slot immediately before the most significant bit of the input digital data stored in the temporary storage circuit in synchronization with the multiplexing control signal. And inserts the frame bits of the first frame pattern at the position of the multiplex control signal to read out the intermediate data. 2. The time division multiplexing circuit according to claim 1, further comprising a first multiplexing circuit for generating digital data. A second frame pattern generator responsive to the multiplexed clock for generating frame bits of the second frame pattern every 2M clocks; A timing signal generator which responds to generate a timing signal at the position of the stuff bit, and alternately reads the additional information bit and the frame bit of the second frame pattern at the position of the stuff bit by the timing signal, and 3. The time-division multiplexing circuit according to claim 2, further comprising a second multiplexing circuit that multiplexes with the digital data and generates the multiplexed data. 4. The method according to claim 1, wherein the frame bits of the first frame pattern are generated every nine clocks of the missing clock obtained by removing the multiplexed clock every M clocks, and the input digital data in the multiplexed data is generated. 2. The time-division multiplexing circuit according to claim 1, wherein said time-division multiplexing circuit is arranged in a time slot immediately before said most significant bit. 5. The time division multiplexing circuit according to claim 4, wherein said M is 11.