JPH0350467B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a pulse staff synchronizer, a staff control signal is used to control the generation of a reset pulse in a phase comparator circuit, thereby achieving synchronization due to jitter in an input signal. This eliminates the negative influence on the determination of whether or not staff control is necessary.

[Industrial application field]

The present invention relates to an improvement in a pulse staff synchronization method for asynchronous digital signals used in a digital multiplex converter.

For example, multiple input low-speed PCM signals that are asynchronous to each other are synchronized and multiplexed to create one synchronous multiplex.
When configuring the PCM signal, select the clock frequency of the multiplexed PCM system to be slightly higher than the clock frequency of the low-speed PCM, and synchronize by inserting additional bits into the low-speed PCM on the transmitting side by the frequency difference between the two. , the receiving side restores the original low-speed PCM by removing the additional bits.

FIG. 3 shows an example of such a pulse staff synchronization circuit in a block circuit diagram.

In the figure, 1 is the memory, 2 is the write counter, and 3
is a read counter, 4 is a phase comparison circuit, 5 is a staff judgment circuit, and 6 is an AND gate.

The low-speed PCM signal is written into the memory 1 by the output of the write counter 2 and temporarily stored. The stored data is read and synchronized with the output of the read counter 3, which is a multiplexed PCM clock signal selected at a slightly higher frequency, and fed to the multiplexed PCM system.

The phase comparator circuit 4 on the transmitting side of the staff-synchronized multiplexed PCM system is a circuit that monitors the difference between the phase of the write clock and the phase of the read clock to the memory 1, and monitors the phase difference when the phase difference reaches a predetermined value. When this occurs, the staff judgment circuit 5 judges that it is necessary to insert an additional pulse, and at the same time sends the insertion position information of the additional pulse to the receiving side of the system, the read prohibition gate 6 detects the above-mentioned A pulse for inhibiting the read operation of the memory 1 by the output of the read counter 3 that counts the multiplexed PCM clock is sent by the amount of the additional pulse inserted.

Since the phase comparison circuit is an important circuit for staff synchronization, it is desirable that it always function correctly even if there is phase jitter in the input low-speed PCM signal.

[Conventional technology]

FIG. 4 shows an example of a conventional phase comparison circuit used in a staff synchronizer, and FIG. 5 is a waveform time chart for explaining its operation.

In the figure, 11, 21 and 22 are D-flip-flop circuits.

A write timing signal 12 based on the output of the write counter 2 and a read timing signal 13 based on the output of the read counter 3 for the memory 1 shown in FIG. becomes low level.

Signal 14 is connected to the set input S of latch circuit 21. The level H/L of the Q output terminal of the latch circuit 21 is read by an external input phase comparison read timing signal (hereinafter referred to as PCR signal) 16, and is sent to the D input terminal of the flip-flop 22, which is a staff control signal generation circuit. input. and the same
When the PCR signal is input to the C input terminal, the level H/L of the D input terminal of the flip-flop 22 is outputted to its Q output terminal, thereby determining whether or not to insert an additional pulse for staff synchronization.

In FIG. 5, the first column shows the insertion position of the PCR signal 16, and the second column shows the insertion position of the stuff pulse.

The insertion position of this stuff pulse is predetermined and fixed.

The third column shows the waveform of the set signal 14 of the latch circuit 21, the fourth column shows the Q terminal output signal of the latch circuit 21, and the fifth column shows the waveform of the Q terminal output signal 23 of the stuff control signal generating circuit, that is, the flip-flop circuit 22.

When the phase difference between the write timing signal and the read timing signal becomes small, the latch circuit 21 is set at the falling transition point of the set signal 14 in the third column from high level to low level, and the Q terminal of the latch circuit 21 is set. Generates a high level signal.

This high level signal is sent from the latch circuit 21.
It is applied to the D input terminal of the flip-flop circuit 22 which is a staff control signal generation circuit, and when this D input terminal is at a high level H, when the external input PCR signal 16 is applied to the C terminal of the circuit 22, the circuit 2
2 generates a high level staff control signal 23 as shown in the fifth column.

However, the PCR signal is also input to the C terminal of the flip-flop circuit 22, which is a staff control signal generation circuit, and outputs a low level L to the opposite polarity output terminal Q, so that the low level output L is output to the latch circuit 21. The high level H stuff control signal 23 applied to the reset terminal R resets the latch circuit 21 and is generated in the flip-flop 22.
is reset to low level L by the next PCR signal.

The sixth column shows the stuff pulse selected from the stuff pulse positions in the second column by the stuff control signal.

In other words, when the phase difference between the write timing signal and the read timing signal decreases, the next PCR starts.
Within one cycle of the signal, one of the stuff pulses whose position is specified in advance is selected and inserted as a stuff pulse.

FIG. 6 is a circuit diagram of another conventional example of a phase comparison circuit used in a staff synchronizer, and FIG. 7 is a waveform time chart for explaining its operation.

In the figure, parts corresponding to those in FIGS. 4 and 5 are indicated by the same numbers.

Note that 24 is a NOR gate and corresponds to the circuit 11. Further, 25 is a latch circuit corresponding to the circuit 21, and the latch circuit is composed of two NOR circuits.

When the phase difference decreases to such an extent that the low level portions of the write signal 12 and read signal 13 overlap, the latch circuit 25 is set and the high level H signal A is transferred to the D flip-flop 22 of the staff control signal generation circuit.
is supplied to the D input terminal of.

When the reset signal 26 is applied to the latch circuit 25, the latch circuit 25 is reset.

The timing for applying the reset signal is set between the insertion position of the stuff pulse and the PCR signal, as shown in FIG.

[Problem that the invention seeks to solve]

In a staff synchronizer, an asynchronous digital signal is input via a transmission line and often contains jitter. Therefore, it is difficult for the phase comparison circuit to operate normally if the write clock signal contains jitter.

In the conventional circuit shown in FIG. 4, since the latch circuit 21 is reset by the sign-inverted signal of the stuff control signal 23 generated in the circuit 22, two consecutive frames cannot be stuffed. Therefore, there is a drawback that the followability to input jitter is poor.

In addition, in the conventional example shown in Fig. 6, since the latch reset signal is placed before the PCR signal, there is a risk that if the phase difference between the write timing signal and the read timing signal changes due to jitter, it will be determined that there is no need for staff control. There is a problem.

[Means for solving problems]

The above problem is caused by multiple low-speed inputs that are asynchronous to each other.
Write clock 1 to memory 1 of each PCM signal
2 and the read clock 13 of the memory set at a speed slightly faster than the write clock, it is determined whether or not to insert a stuff pulse for synchronization, and the read operation is performed by the number of insertion pulses determined to be necessary. In a pulse stuff synchronizer which inhibits reading of the memory by a clock, inserts a stuff pulse to perform synchronization, and outputs the clock to a multiplexing system, an OR gate 24 which compares the phases of the write clock 12 and the read clock 13 is used. , a latch circuit 25 whose output state A is set to high level H by the output signal of the OR gate, and an output signal A of the latch circuit.
Input the external input phase comparison read timing
Flip-flop 22 output by PCR16
and an external input reset pulse 2 for setting the staff control signal 23 which is the output of the flip-flop and the output A of the latch circuit 25 to the low level L.
6, the output of the AND gate 27 is used as the reset input B of the latch circuit 25, and the input phase of the reset pulse 26 is determined by a separately fixed stuff pulse insertion position. Phase comparison reading timing from PCR16
The flip-flop 22 is set between
Only when the staff control signal 23, which is the output signal of the This problem is solved by the pulse staff synchronizer of the present invention, which is configured so that a control signal is output, a pulse is inserted, and synchronization is achieved.

[Effect]

In the phase comparison circuit of the pulse staff synchronizer of the present invention, the output signal of the AND gate 24 which compares the phases of the write clock 12 and the read clock 13 of the memory 1 becomes the set input of the latch circuit 25, and the output signal of the latch circuit 25 is set. Set state A to high level H. In addition, the output signal A of high level H is inputted, and a stuff control signal 23 which is the output of the flip-flop 22 which is output in response to the timing signal PCR of the external input and a reset pulse 26 of the external input are input.
The output of the AND gate 27 which takes the product of the latching circuit 25 is set as the reset input B which sets the output state A of the latch circuit 25 to a low level L. That is, the output signal A of the latch circuit 25 is inputted, and the reset pulse 26 of the external input is controlled by the AND gate 27 using the stuff control signal 23 of the output of the flip-flop 22 which is output in response to the timing signal PCR of the external input. hand,
Controls generation of reset input B to latch circuit 25. As a result, the reset pulse is prohibited in the level L state where no pulse is generated at the predetermined staff pulse insertion position, and in this prohibited state, the phase of the write pulse and the read pulse are close to each other and the latch circuit is set. Since the signal is held until a stuff pulse is inserted, there is no possibility of reading errors due to jitter. Furthermore, when the stuff is inserted, even if the latch circuit is reset by the generation of a reset pulse, if the write pulse and read pulse approach within a predetermined phase difference, the latch circuit will be reset again, so that Statuf is possible.

〔Example〕

The gist of the present invention will be explained in detail according to the illustrated embodiments.

FIG. 1 shows a block diagram of an embodiment of the phase comparison circuit, and FIG. 2 is a waveform diagram for explaining the operation of the circuit.

In FIG. 1, the same parts as in FIG. 6 are designated by the same numbers. In the embodiment of the present invention, an AND circuit 27 is provided at the reset input of the latch circuit 25, and outputs the reset pulse 26 and the staff control signal generating circuit 2.
The AND output B with the staff control signal 23, which is the output signal of the latch circuit 2, is used as a reset input.
5.

The operation of the circuit is as follows.

The latch circuit 25 is set when the phase difference between the write pulse 12 and the read pulse 13 input to the NOR gate 24 decreases, and supplies the fifth column signal A to the staff control signal generation circuit 22. In this state, when the first column PCR signal 16 is applied to the clock input terminal C of the circuit 22, the sixth column staff control signal is generated. However, before the PCR signal is applied, the third column reset pulse 26 is applied to the AND gate 27. This reset pulse 26 is generated because the staff control signal 23 has not yet been generated.
AND gate 27 prevents this from causing the latch circuit to reset. Therefore, latch circuit 25 holds a stable set signal and transfers it to circuit 2.
Continue to give to 2. Therefore, the staff control signal for the sixth column can be reliably generated by the next PCR signal.

When the staff control signal is generated, AND gate 2
7 allows the reset pulse 26 to pass.

The reset input B of the fourth column, which is the AND output of the reset pulse 26 of the third column and the staff control signal 23 of the sixth column, is applied to the latch circuit 2 as a reset signal.
5 and can reset the latch circuit 25.

When the latch circuit 25 is reset, the staff control signal 23, which is the output of the flip-flop 22, is reset.
changes from high level H to low level L as shown in the sixth column by the next PCR signal.
In response to the stuff control signal 23, the stuff pulse of the seventh column, which is one of the stuff pulses at the stuff pulse insertion position of the second column, is inserted. but,
Even if the latch circuit 25 is temporarily reset by the reset pulse 26 of the third column and the output A of the fifth column is set to low level L, the positions of the write clock 12 and read clock 13 remain unchanged. If the phase difference is small, the output A of the fifth column immediately returns to high level H, and the staff control signal 23 of the sixth column also changes to the next level.
It is maintained at high level H by the PCR signal. Therefore, even in the interval between the next PCR signal, the stuff pulse of the seventh column is inserted, and continuous stuffing can be performed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform normal staff synchronization even when the input signal contains jitter, and it is also possible to insert staff in two consecutive frames, which is useful for synchronous multiplexing of digital signals. On the other hand, the effect of improving the reliability of the operation is extremely large.

[Brief explanation of drawings]

Fig. 1 is a block diagram of one embodiment of the phase comparison circuit, Fig. 2 is a waveform diagram for explaining the circuit operation, Fig. 3 is a block diagram of the pulse staff synchronizer, and Fig. 4 is a block diagram of the staff synchronizer. A circuit diagram showing an example of a conventional phase comparison circuit used, FIG. 5 is a waveform time chart for explaining its operation, and FIG. 6 is a circuit diagram showing another example of a conventional phase comparison circuit used in a staff synchronizer. 7 are waveform time charts for explaining the operation. In the figure, 1 is memory, 2 is write counter,
3 is a reading counter, 4 is a phase comparison circuit, 5 is a staff judgment circuit, and 6 is an AND gate. 11,
24 is a phase comparison circuit for write and read clocks, 2
1 and 25 are latch circuits, 22 is a staff control signal generation circuit, and 27 is a reset pulse gate circuit.

Claims (1)

[Claims] 1. The phase between the write clock 12 of each of the plurality of mutually asynchronous input low-speed PCM signals to the memory 1 and the read clock 13 of the memory set at a slightly higher speed than the write clock. Based on the comparison output, it is determined whether or not it is necessary to insert a stuff pulse for synchronization, and the read clock is inhibited from reading the memory by the number of insertion pulses determined to be necessary, and the stuff pulse is inserted to synchronize and send to the multiplexing system. The output pulse staff synchronizer includes an OR gate 24 that compares the phases of the write clock 12 and the read clock 13, and a latch circuit 25 whose output state A is set to a high level by the output signal of the OR gate. , a flip-flop 2 which inputs the output signal A of the latch circuit and outputs it according to the external input phase comparison reading timing PCR16.
2, and an external input reset pulse 2 for setting the staff control signal 23 which is the output of the flip-flop and the output A of the latch circuit 25 to low level.
6, and the output of the AND gate 27 is sent to the latch circuit 2.
5, and the reset pulse 2 is
The input phase of No. 6 is the phase comparison read timing from the static pulse insertion position which is fixedly given separately.
The staff control signal 2 is set up to PCR16 and is the output signal of the flip-flop 22.
3 is output and a stuff pulse is inserted, the reset pulse 26 is output to the AND gate 27.
, the latch circuit 25 is reset, and the final staff control signal is output from the flip-flop 22 to achieve synchronization.