JPS61224739A - Pulse stuff synchronizing device - Google Patents

Abstract

PURPOSE:To eliminate adverse effect of signal jitter onto synchronization by using a stuff control signal for the control of generation of a reset pulse of a phase comparator circuit. CONSTITUTION:A latch circuit 25 is set when the phase difference between a write pulse 12 and a read pulse 13 is decreased and applies a signal A to a stuff control signal generating circuit 22. When a phase comparison read timing signal (PCR) 16 is inputted to a clock input terminal of the circuit 22 in this state, a stuff control signal 23 is generated. Before the PCR signal 16 is given, a reset pulse is given to an AND gate 27. Since the reset pulse is blocked by an AND gate 27 since the stuff control signal 23 is not generated yet, resulting that the latch circuit 25 is not reset. Thus, the latch circuit 25 holds a stable set signal, it is kept given to the circuit 22 and the next PCR signal generates surely the stuff control signal.

Description

[Detailed Description of the Invention] [Summary] In a pulse-untuff synchronizer, a stuff control signal is used to control the generation of a reset pulse in a phase comparator circuit, thereby eliminating the negative influence of signal jitter on synchronization. .

[Industrial application field]

The present invention relates to an improvement in a pulse stuff synchronization method for asynchronous digital signals used in a digital multiplex converter.

For example, when multiplexing a low-speed PCM system to configure a multiplexed PC system, the clock frequency of the multiplexed PCM system is selected to be slightly higher than the clock frequency of the low-speed PCH, and the difference in frequency between the two is adjusted on the transmitting side. Low speed PCH
The original low-speed PCM can be restored by inserting an additional bit into the signal for synchronization, and removing the additional bit on the receiving side.

FIG. 3 shows an example of such a pulse temp synchronization circuit in a block circuit diagram.

In the figure, 1 is a memory, 2 is a write counter, 3 is a read counter, 4 is a phase comparison circuit, 5 is a stuff judgment circuit, and 6
is an AND gate.

The low speed PCM signal is written to the memory 1 via the write counter 2 and temporarily stored. The stored data is read by a read counter with the multiplexed PCM clock signal selected at a slightly higher frequency and fed to the multiplexed PCM system.

Since the frequency of the read clock signal is higher than the frequency of the write clock signal, the reading speed is faster and the same data is read twice.

The phase comparator circuit 4 is a circuit that monitors the phase difference between the write phase and the read phase, and when the phase difference approaches O, this is detected, and the stuff determination circuit 5 receives additional pulse insertion position information. The read inhibit gate 6, which sends the multiplexed PCM clock signal to the read counter, inhibits one bit from being read in the next multiplexed frame.

Since the phase comparison circuit is an important circuit for staff synchronization,
It is desirable that it always function correctly.

[Conventional technology]

FIG. 4 shows an example of a conventional phase comparator circuit used in a stuff synchronizer, and FIG. 5 is a waveform time chart for explaining its operation.

In the figure, 11, 21, and 22 are D-flip-flop circuits.

A write timing signal and a read timing signal are input to the flip-flop 11, and when the phase difference between the two is small, the output 14 becomes a low level.

The signal 14 is connected to the set input S of the latch circuit 21. The output of the latch circuit is read by a phase comparison read timing signal (hereinafter referred to as PCR signal) 16 to determine whether or not to insert stuff.

In FIG. 5, the first column shows the insertion position of the PCR signal 16, and the second column shows the insertion position of the stuff pulse.

The insertion position of this stuff pulse is predetermined and fixed.

The third column shows the waveform of the set signal 14 of the latch circuit 21, the fourth column shows the Q terminal output signal of the latch circuit 21, and the fifth column shows the waveform of the Q terminal output signal 23 of the stuff control signal generation circuit, that is, the flip-flop circuit 22.

When the phase difference between the write timing signal and the read timing signal becomes small, the latch circuit 21 outputs the set signal 1 of the third column.
It is set at the falling conversion point from high level to low level in No. 4, and a high level signal is generated at the Q terminal of the latch circuit 21.

This high level signal is applied from the latch circuit 22 to the D input terminal of the flip-flop circuit 22, and when the D input terminal is at high level and the PCR signal 16 is applied to the T terminal of the circuit 22, the circuit 22 A high level stuff control signal 23 as shown in column 5 is generated.

However, since the PCR signal inverts the output of the launch circuit 21 and makes the Q output low level, the flip-flop 2
The stuff control signal generated in step 2 is reset by the next PCR signal.

The sixth column shows stuff pulses selected from the stuff pulse positions of the second column by the stuff control signal.

That is, when the phase difference between the write timing signal and the read timing signal decreases, one of the stuff pulses whose position is specified in advance is selected and inserted as a stuff pulse within one cycle of the next PCR signal. Ru.

FIG. 6 is a circuit diagram of another conventional example of a phase comparison circuit used in a stuff synchronizer, and FIG. 7 is a waveform time chart for explaining its operation.

In the figure, parts corresponding to those in Figure 4.5 are indicated by the same numbers.

Note that 24 is a NOR gate and corresponds to the circuit 11.

Further, 25 is a launch circuit corresponding to the circuit 21, and the launch circuit is composed of two NOR circuits.

When the phase difference decreases to such an extent that the low level portions of the write signal 12 and read signal 13 overlap, the latch circuit 25 is set and a high level signal is supplied to the stuff control signal generation circuit 22.

When the reset signal 26 is applied to the latch circuit 25, the latch circuit 25 is reset.

The timing for applying the reset signal is set between the insertion position of the stuff pulse and the PCR signal, as shown in FIG.

[Problem that the invention seeks to solve]

In a stuff synchronizer, an asynchronous digital signal is input via a transmission line and contains a large amount of jitter. Therefore, it is difficult for the phase comparator circuit to operate normally if the write clock signal includes jitter.

In the conventional circuit shown in FIG. 4, since the latch circuit 21 is reset by the stuff control signal 23, it is not possible to stuff two consecutive frames. Therefore, there is a drawback that the ability to follow the input pitch is poor.

Furthermore, in the conventional example shown in FIG. 6, since the launch reset signal precedes the PCR signal, there is a risk that it will be determined that there is no stuffing when the phase difference between the write timing signal and the read timing signal changes due to jitter. That's a problem.

[Means for solving problems]

The problem mentioned above is that the set input is the NAND of the write clock signal and the read lock signal, and the AND of the reset signal and the output signal of the flip-flop circuit whose output signal is supplied together with the timing signal is the reset input. The problem is solved by the pulse-stuff synchronizer of the present invention, which includes a latch circuit.

[Effect]

According to the present invention, the generation of the reset pulse is controlled by the stuff control signal. As a result, the reset pulse is prohibited in a state where a stuff pulse is not generated, and this disabled state is maintained until the phases of the write pulse and read pulse become close and the latch circuit is set and a stuff pulse is inserted. Therefore, reading errors due to the shifter will not occur.

In addition, when the stuff insertion state is entered, even if the latch circuit is reset by the generation of a reset pulse, if the write pulse and read pulse approach each other within a predetermined phase difference, the latch circuit will be set again, so that continuous The staff is available.

〔Example〕

The gist of the present invention will be explained in detail according to the illustrated embodiments.

FIG. 1 shows a block diagram of an embodiment of the phase comparator circuit, and FIG. 2 is a waveform diagram for explaining the circuit operation.

In FIG. 1, the same parts as in FIGS. 1 and 6 are designated by the same numbers. In the embodiment of the present invention, the AND circuit 27 is the latch circuit 2
The logical product of the reset pulse 26 and the output signal of the stuff pulse generation circuit 22, that is, the stuff control signal, is supplied to the latch circuit 25.

The operation of the circuit is as follows.

The launch circuit 25 is set when the phase difference between the write pulse and the read pulse decreases, and supplies the fifth column signal to the stuff control signal generation circuit 22. In this state, when the first column PCR signal is applied to the clock input terminal of the circuit 22, the sixth column
Generates column stuff control signals. However, before the PCR signal is applied, a third column reset pulse is applied to the AND gate 27. This reset pulse is blocked by AND gate 27 since the stuff control signal has not yet been generated, so that it will not reset the latch circuit. Therefore, the latch circuit 25 holds a stable set signal,
This continues to be supplied to the circuit 22. Therefore, the stuff control signal for the sixth column can be reliably generated by the next PCR signal.

When the stuff control signal is generated, AND gate 27 passes reset pulse 26.

The AND signal of the reset pulse in the third column and the stuff control signal in the sixth column and the signal in the fourth column are applied to the latch circuit 25 as a reset signal, so that the latch circuit 25 can be reset.

When the latch circuit is reset, the stuff control signal changes from high level to low level as shown in the fifth column by the next PCH.

One stuff pulse at the stuff pulse insertion position in the second column, the seventh column, is inserted by the stuff control signal.

However, even if the latch circuit is reset by the reset pulse in the fourth column, if the phase difference between the clock signals 12 and 13 is still small, the signal in the fifth column immediately returns to high level, and the stuff control signal Also next PC
It is maintained at a high level by the R signal.

Therefore, a stuffing pulse is inserted in the next PCR signal section, and continuous stuffing can be performed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform normal stuff synchronization even when the signal contains jitter, and it is also possible to insert stuff for two consecutive frames, which is useful for synchronous multiplexing of digital signals. , its effects are extremely large.

[Brief explanation of drawings]

Fig. 1 is a block diagram of one embodiment of the phase comparison circuit, Fig. 2 is a waveform diagram for explaining the circuit operation, Fig. 3 is a block diagram of the pulse tap synchronization circuit, and Fig. 4 is the stuff synchronization device. Figure 5 is a waveform time chart for explaining its operation; Figure 6 is a circuit diagram showing an example of a conventional phase comparison circuit used in a stuff synchronizer. The circuit diagram and FIG. 7 are waveform time charts for explaining its operation. In the figure, 1 is a memory, 2 is a write counter, 3 is a read counter, 4 is a phase comparison circuit, 5 is a stuff judgment circuit, and 6 is an AND gate. 11.24 is a write and read lock phase comparison circuit, 2
1.25 is a latch circuit, 22 is a stuff control signal generation circuit, and 27 is a recent pulse gate circuit. Suta, Fuha Rusuma 4 Zomei 1
2 Phantom Dimension Rus Staff (EHIIi 4 eyes 4 block lo inferior 3 hindrance

Claims (1)

[Claims] A latch circuit whose set input is the phase comparison output of the write clock signal and the read lock signal, and whose reset input is the logical product of the output signal of the flip-flop circuit (22) whose output signal is supplied together with the timing signal and the reset signal. (25) A pulse stuff synchronizer characterized by comprising: (25).