JPH0556699B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a synchronization circuit for synchronizing information serially transmitted in a single signal line connected to a digital communication device, and in particular to a reset counter type that does not include a synchronization protection circuit. This relates to a synchronous circuit. [Prior Art] Fig. 3 is an electrical circuit diagram showing a conventional reset counter type synchronization circuit. A selector as a counter operation switching circuit receives the carry pulse of the counter 1 at the "0" input terminal, selects one of these signals, and supplies an output to the reset input terminal of the counter 1. 7 is a counter. Exclusive OR gate (EX-
8 is an AND gate into which the carry pulse of counter 1 and the inverted signal of clock T are input; 6 is an AND gate that receives the output of AND gate 8 at the clock end, and the output of exclusive OR gate 7 at the data input end. It is a rising edge type D flip-flop that receives Note that the positive logic output terminal of the flip-flop 6 is connected to the selection control input terminal of the selector 2. The flip-flop 6 also outputs a signal _S1 indicating the synchronization state. Next, the operation will be explained. FIG. 4 is a time chart showing waveforms of various parts of a synchronous circuit with a period of 4, for example. When a clock T as shown in FIG. 4a is applied to counter 1, counter 1 is
It assumes a numerical state as shown in FIG. 4, and outputs a carry pulse as shown in FIG. 4c at cycle 4. Now, assuming that synchronization is achieved up to time t ₀ ,
The synchronization signal shown in FIG. 4d and the carry pulse shown in FIG. 4c match, and the output waveform of the exclusive OR gate 7 shown in FIG. 4e and the output waveform of the flip-flop 6 shown in FIG. 4g indicates a logic "0", and the selector 2 outputs the carry pulse (see FIG. 4c) inputted to the "0" input terminal to the counter 1. As a result, in the synchronous state, the counter 1 increments in a self-loop. That is, the counter 1 is in a free running state. Next, the synchronization signal shown in FIG. 4d is applied from time t ₀ to t ₁
If a slip or the like occurs during the synchronization, the carry pulse shown in Fig. 4c and the synchronization signal shown in Fig. 4d do not match at time _t2 , so the exclusive logic The output of sum gate 7 is logic “1”
become. As a result, the AND gate 8 which performs the logical product of the carry pulse and the clock shown in FIG.
An out-of-synchronization state is stored in the flip-flop 6 with the output waveform (see FIG. 4f). In this state, the [1] input terminal of the selector 2 is selected, and the synchronizing signal shown in FIG. 4d is output to the counter 1, and the phase is regulated at time _t3 . It becomes operational and returns to the synchronized state. In addition, the output of selector 2 is shown as follows:
The result will be as shown in Figure 4h. [Problem to be solved by the invention] However, in the conventional synchronous circuit, when the signal line is disconnected and the synchronous signal is fixed to logic 0, the synchronous state signal _S1 goes out of synchronization only once in one cycle. , and the rest are incorrectly shown as being in sync. Conversely, even if the synchronization signal is fixed at logic 1, the synchronization state and the out-of-synchronization state are repeated, and there is a risk that erroneous data may be received during this period. The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a synchronization circuit that can detect an abnormality in a synchronization signal within one cycle. [Means for Solving the Problems] A synchronous circuit according to the present invention includes a counter and a counter operation switching circuit that puts the counter in a free-running operation state or puts it in a regulated operation state according to a synchronous signal. A shift register is provided to store one cycle of , and the state of the counter and the state of the shift register are input to generate an output logic for a set of input patterns that can be taken in a synchronous state and a set of input patterns that can be taken in an asynchronous state. A synchronization determination circuit having different values is provided, and a flip-flop is provided for storing the output of the synchronization determination circuit and controlling the counter operation switching circuit. That is, the synchronous circuit according to the present invention is a conventional synchronous circuit added with a shift register that stores a synchronous signal sequence for one past cycle and a synchronization determination circuit. [Operation] In the synchronous circuit according to the present invention, the state of the counter and the state of the shift register are input to the synchronization determination circuit, and in the synchronous state, for example, a "0" output is input to the flip-flop. As a result, the flip-flop controls the counter operation switching circuit to put the counter in a free running state. Next, when an asynchronous state occurs, an output of, for example, "1" is input from the synchronization determination circuit to the flip-flop. As a result, the flip-flop controls the counter operation switching circuit in order to bring the counter into the normal operation state according to the synchronization signal. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. In Figure 1, 1 is a counter that receives the clock T, and 2 receives the synchronizing signal Ss at the ``1'' input terminal, receives the carry pulse of counter 1 at the ``0'' input terminal, and selects between these signals. Select counter 1 with
A selector serves as a counter operation switching circuit that outputs to the reset input terminal of the counter 1 to put the counter 1 into a free-running operation state or a regulated operation state by a synchronization signal, and 3 is a clock set to be shorter by 1 than the period of the synchronization signal Ss. A shift register that stores one period of the synchronization signal Ss by receiving T and the synchronization signal Ss, 4 is an output indicating the state of the counter 1, a parallel output of the shift register 3, and the synchronization signal Ss
This synchronization determination circuit 4 is configured by combining logic gates, etc.
As mentioned above, in response to the state of counter 1, the state of shift register 3, and the synchronization signal Ss, the output logic value is set to be different for the set of input patterns that can be taken in the synchronous state and the set of input patterns that can be taken in the asynchronous state. It is configured. In addition, the synchronization signal Ss, the state of shift register 3,
An example of the output (truth table) of the synchronization determination circuit 4 according to the state of the counter 1 is shown in the following table.

〔Effect of the invention〕

As described above, according to the present invention, a synchronization determination circuit is provided and the synchronization/asynchronous state is determined based on the pattern of the counter state and one cycle of synchronization signal string from the shift register, so that synchronization abnormality is detected. can be detected within one cycle, which has the effect of eliminating data errors due to synchronization errors.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram showing a synchronous circuit according to an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the invention, and Fig. 3 is an electric circuit diagram showing a conventional synchronous circuit. , FIG. 4 is a time chart explaining the operation of a conventional synchronous circuit. In the figure, 1...Counter, 2...Selector, 3...Shift register, 4...Synchronization determination circuit, 5...Flip-flop. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1 includes a counter and a counter operation switching circuit that puts the counter into a free-running operation state or puts it into a regulated operation state using a synchronization signal, and is provided with a shift register that stores one cycle of the synchronization signal; and the state of the shift register, a synchronization determination circuit having different output logical values for a set of input patterns that can be taken in a synchronous state and a set of input patterns that can be taken in an asynchronous state is provided, and the synchronization determination circuit A synchronous circuit characterized in that a flip-flop is provided for storing the output of the circuit and controlling the counter operation switching circuit.