JPS63232536A - Synchronous circuit - Google Patents

Abstract

PURPOSE:To detect the abnormality of synchronization within one period by deciding synchronizing and asynchronizing states by the pattern between the state of a counter and the synchronizing signal train in one cycle from a shift register. CONSTITUTION:The shift register 3 is set by one shorter than the cycle of the synchronizing signal Ss and stores one period of the synchronizing signal Ss by receiving a clock T and the synchronizing signal Ss. The state of the counter 1 and that of the shift register 3 are inputted in a synchronization deciding circuit 4 and in the case of asynchronous state the synchronization deciding circuit 4 outputs one output, for example, then a flip flop 5 controls a selector 2 in order to make the counter 1 in a specified action state by the synchronizing signal Ss. Thus, the abnormality of synchronization can be directly detected and the error of data to the error of synchronization can be removed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synchronization circuit for synchronizing information serially transmitted in a single signal line connected to a digital communication device, and in particular, This invention relates to a reset counter type synchronous circuit that does not include a synchronous protection circuit.

[Conventional technology]

FIG. 8 is an electric circuit diagram showing a conventional reset counter type synchronous circuit, and in this FIG. 8, (1) /f
i Counter receiving clock T, (2) is synchronization signal Ss
is received at the ``1'' input terminal, and the counter (υ) is received at the ``0'' input terminal. Selector as a counter operation switching circuit, (7) is an exclusive OR gate (EX-OR gate) into which the digit pars of the counter (1) and the synchronization signal are input, (8) is the digit of the counter (1) 14j pares and clock T inversion ti
The AND gate (6) receives the output of the AND gate (8) at the clock end, and the D flip-flop of the rising edge type receives the output of the exclusive OR gate (7) at the data input end. be. The positive logic output terminal of the flip-flop (6) is connected to the selection iti1m input terminal of the selector (21).The flip-flop (6) also outputs a signal @S1 indicating the synchronization state. It has become.

Next, the operation will be explained. FIG. 4 is a time chart showing waveforms of various parts of a synchronous circuit with a period of 4, for example. When the counter (1) is applied with a lock T as shown in FIG. The state of the numerical value as shown in FIG. 4(b) is taken, and a digit E offset pulse as shown in FIG. 4(c) is output in cycle 4.

Now, time t. Assuming that synchronization is achieved at t, the synchronization shown in @4 (d) is the number and the digit t gap shown in Figure 4 (C).
The output waveform of the exclusive disjunctive gate (7) shown in No. 411ffl(e) and the output waveform of the flip-flop (6) shown in FIG. 4(g) show logic "0",
The selector (2) outputs the digit shift pulse input to the "0" input terminal (see Figure 4 (c)) to the counter (υ).As a result, in the synchronous state, the counter (1) The counter (υ) is in a free running state.

Next, from time to to tl in synchronization number 1 shown in FIG. 4(d).
If a slip or the like occurs during this time and an out-of-synchronization occurs, the carry parse shown in Figure 4(c) and the synchronization number shown in Figure 4(d) will not match at time 't2. Therefore, the output of the exclusive OR gate (7) becomes logic rlJ. As a result, the output waveform of the AND gate (8) which is the logical product of the carry pattern t shown in No. 4m(c) and the clock T [see No. 41/(f)] is obtained from the flip-flop (6).
The out-of-synchronization state is memorized. In this state, the Cxr input terminal is selected as the input of the lid (2), and the
Synchronization 1 shown in d)! The number is output to the counter (1),
At time t3, the phase is regulated, that is, the counter (1) enters the regulated operation state by the synchronization signal and returns to the synchronous state. The output of selector (2) is shown in Fig. 4 (h).
become that way.

[Problem that the invention seeks to solve]

However, in the conventional synchronous circuit, when the signal line is disconnected, the synchronization signal is fixed to logic 0, and the synchronization state signal 5III'118ail shows an out-of-synchronization only once.
The rest may be incorrectly indicated as a synchronous state, or conversely, even if the synchronous signal is fixed at logic 1, the synchronous state and out-of-synchronization state will repeat, and erroneous data may be received in the dark.

This invention was made in order to solve the problems mentioned in item t above, and its purpose is to eliminate an abnormality in the synchronization signal by a synchronization circuit that can be used within one cycle.

[Means for resolving gaps]

A synchronous circuit according to the present invention includes a counter, a counter operation switching circuit that puts the counter into a free-running operation state or a regulated operation state according to a synchronization signal, and a shift register that stores one cycle of the synchronization signal. At the same time, a synchronization judgment is performed in which the output logic value is different for a set of input patterns that can be taken in a synchronous state and a set of input patterns that can be taken in an asynchronous state by inputting the shape of the counter and the state of the shift register T. In addition, a flip-flop is provided to store the output of the synchronization determination circuit and control the tth counter operation 17JIK circuit.

That is, the synchronous circuit according to the present invention is a conventional synchronous circuit in which a shift register for storing the synchronous @ code sequence for one past period and a synchronization determination circuit are added.

[For production]

In the synchronous circuit according to the present invention, the state of the counter and the state of the shift register are input to the synchronization determination circuit, and in the synchronous state, for example, the rOJ output is input to the flip-flop. As a result, when the flip-flop enters a zero-order asynchronous state in which the counter operation switching circuit is controlled so as to put the counter in a free-running state, an output of, for example, "1" is input from the synchronization determination circuit to the flip-flop. As a result, the flip-flop controls the counter operation switching circuit in order to bring the counter into the regulated operation state according to the synchronization signal.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, (1) is a counter that receives clock T, and (2) receives synchronous No. 16 Ss at the rlJ input terminal, and receives the digit I:&f of counter (1) at the "0" input terminal. By selecting one of these signals and outputting it to the reset input terminal of the counter (1), the counter (1) can be put into a free running state or controlled by a synchronizing signal. :Selefter as a counter operation switching circuit that sets the operating state, (3)
is a shift register that is set to be 1 shorter than the period of the synchronization signal Ss and stores one period of the synchronization signal @SS by receiving the clock T and the synchronization signal @Ss, and (4) is a counter (
This is a synchronization judgment circuit to which the output indicating the state of 1), the parallel output of the shift register (3), and the synchronization signal @SS are input, and this synchronization judgment circuit (4) is constructed by combining logic gates, etc. As described above, in response to the state of the counter (1), the state of the shift register (3), and the synchronization signal Ss, an output logical value is output for a set of input patterns that can be taken in a synchronous state and a set of input patterns that can be taken in an asynchronous state. are configured differently.

In addition, the synchronous signal @Ss and the state of the shift register (3).

An example of the output of the synchronization determination circuit (4) according to the state of the counter 11 (when the truth is 2, the result is 1 as shown in the table below).

(6) receives the output from the synchronization discrimination circuit (4) at the set input terminal S, receives the digit loss pass of the counter (1) at the reset input terminal R, and sends the positive logic output to the selector (2). This is a flip-flop that outputs to the selection input terminal. Note that the flip-flop (5) is configured to output a signal @st indicating a synchronized state to a display means (not shown).

Next, the synchronous circuit of this embodiment having the above-mentioned configuration will be explained with reference to FIG. 2 which shows a time chart representing the signals of the main parts divided into FIG. 1.

Figure 2 is an example of a synchronous circuit with a period of 4. When a clock T with a waveform as shown in Figure 2 (a) is applied to the counter (1), the counter (υ is as shown in Figure 2 (b)). It assumes the numerical state shown in , and outputs a digit slipping pass at cycle 4 [see Section 2 (C)].

Assuming that synchronization is now established at time to''1, the input pattern of synchronization judgment time i (4) follows the normal pattern shown in the table above in sequence. Therefore, the synchronization judgment shown in FIG. 2(e) As is clear from the above table, the output waveform of the circuit (4) outputs a logic "0".

In this case, the flip-flop (5) is not set and therefore the selector (2) outputs the carry pass input to the "0" input terminal, so the counter (1)
Progressing with rape. The counter l is in a self-running state.

Next, as shown in FIG. 2(a) Iζ, if a slip or the like occurs in the synchronization signal Ss between time to and tl, and an out-of-synchronization occurs, the input pattern of the synchronization determination circuit (4) is Since the difference is 1 fJ, the output waveform is as shown in Figure 2 (e).
As shown in 1! Therefore, the flip-flop (5) is set as shown in waveform 21a(f) and becomes out of synchronization.

In this way, the positive logic output waveform of flip-flop (5) [
(see Figure 2(f)) is changed to rlJ, selector (2)
selects the synchronous lRe5s of the "1" input terminal and counters (1)
A waveform as shown in FIG. 2(g) is output.

Then, at time t4 following time t1, the counter (1) is reset by the synchronization CM number Ss from the selector (2).

After that, the counter (1) continues to walk, and when a par-less occurs, the flip-flop (5) is reset and the out-of-synchronization state is released, thereby causing the selector (2
The output of 7 becomes a carry-pass output through the ``0'' input terminal again, and as a result, synchronization is restored and the counter (1) continues to increment in a self-rape manner.

In this way, synchronization abnormalities can be detected immediately, thereby making it possible to eliminate data errors caused by synchronization errors.

Note that in the Hongji embodiment, a combination of logic gates is used as the synchronization determination circuit for determining the synchronization state, but a circuit using a read-only memory may also be used.

〔Effect of the invention〕

As described above, according to the present invention, a synchronization determination circuit is provided to determine the synchronization/asynchronous state based on the pattern of the counter state and one cycle of synchronization signal string from the shift register. Abnormalities can be detected within one cycle, which has the effect of eliminating data errors due to synchronization errors.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram showing a synchronous circuit according to an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the invention, and Fig. 8 is an electric circuit diagram showing a conventional synchronous circuit. , FIG. 4 is a time chart illustrating the operation of a conventional synchronous circuit. In the following, (l)...Counter, (2).°Selector 1 (3)...Shift register, (4)...Synchronization judgment time M% 15) -゛°Flip-flop. In addition, in the figure, the same symbol indicates 14-1 or a corresponding portion.

Claims (1)

[Claims] A shift register is provided, which includes a counter and a counter operation switching circuit that puts the counter into a free-running operation state or puts it into a regulation operation state using a synchronization signal, and stores one cycle of the synchronization signal, and also changes the state of the counter. A synchronization determination circuit is provided which outputs different logic values for a set of input patterns that can be taken in a synchronous state and a set of input patterns that can be taken in an asynchronous state by inputting the state of the shift register; A synchronous circuit comprising a flip-flop that stores an output and controls the counter operation switching circuit.