SU1228276A1 - Counter for subtraction - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to expand the functionality. The counter contains a synchronization block I, a shift register 2, a binary subtractor 3, delay elements 4-6, elements 7-10 AND, elements 11 and 12 OR, element 13 NOT, an element EXCLUSIVE OR 14, generators 15 and 16 of single pulses and information inputs 17 and 18. The description of the block diagram of the block I synchronization. Introduction to the device of single pulse generators, the EXCLUSIVE OR element, the OR element 12, and the formation of new connections with the elements of the device allows counting simultaneously via two channels. 2 Il. 1 tab. (L to to CX) th od ft

Description

1The invention relates to automation and computing technology is intended to subtract from the decimal number of two pulse sequences and can be used in various fields of engineering and industry to build discrete automation devices, digital computing devices and devices measuring residual stock in the process of consumption of the same type of production of any physical of nature.

The purpose of the invention is the expansion of functional capabilities by simultaneous counting through two channels.

FIG. 2 is a block diagram of a meter for subtraction; figure 2 - block diagram of the synchronization unit.

The subtraction counter contains a synchronization block 1, a shift register 2, a binary subtractor 3, delay elements 4-6, elements 7–10 AND, elements 11 and 12 OR, element 13 NOT, an element EXCLUSIVE OR 14, generators 15 and 16 single pulses 5 informational inputs 17 and i 8..

The first, second and third outputs of the synchronization unit 1 are connected to the synchronization, data input and control inputs of the shift register 2, respectively, the output of which is connected to the input of the binary binary calculator. The information input of the shift register 2 is connected to the output of element 7 PI, the first input of which is connected through the delay element 4 to the output of element 8 I. The output of the binary subtractor 3 difference is connected to the first input of element 9 AND and through the delay circuit 5 to the first input of the element 8 Hj the second input of which is connected to the output of the element 13 NOT and with the second input of the element 7 I. The input of the deductible binary subtraction 3 is connected to the output of the element 11 Ely first input of which is connected to the output of the delay element 6. The fourth synchronization block I is connected to the second input of element 9 I, the output of which is connected to the input of element NO 13. A binary loan output 3 is connected to the first input of element 12 OR, the output of which is connected to the input of delay element 6. The fifth output of the block I synchronization is connected to the synchronization inputs of the generators 15 and 16 single

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control inputs, which are connected to information inputs 17 and 18 of the counter for subtraction, respectively. The second input of the element 1 1 -shi is connected to the output of the element EXCLUDE- DfEE 1-PCT 14, the first input of which is connected to the first input of the element 10 I and to the code of the generator 15 of single M Gauls. The output of the generator 16 of a single pulse is connected to the second inputs of the EXCLUSIVE OR 14 element and the AND element 10, the output of which is connected to the second input of the OR element 12.

The synchronization unit (Fig. 2) contains a clock pulse generator 19, a pulse distributor 20, a single pulse generator 21, .5 -trigger 22, OR elements 23 and 24, switches 25-28, output buses 29- 335 which are the first, second, third-1, fourth and fifth outputs of the synchronization block, respectively.

The output of the generator 19 clock pulses is connected to the input of the distributor 20 pulses, the output of the last P-th bit of which is connected to the synchronization input of the generator 21 single pulses and the zero input of the trigger 22. The outputs from the first and-and bits of the distributor 20 pulses are connected through a switch 25 with the inputs of element 23 OR. The outputs 4 ix of the bits of the distributor 20 pulses, where i 1,2, .. "T5 and 4t p, are connected to the inputs of the OR element 24, the output of which is connected to the information input of the switch 26. The output of the first bit of the distributor 20 pulses is connected to the information input switch 27. A single trigger input 22 is connected to the output of the oscillator 21 of single ampuls, the control input of which is connected through the switch 28 to the zero signal bus of the counter. The output buses 29–33 of the synchronization unit 1 are connected to the inputs of the generator 19 clock pulses, the OR element 23, the trigger 22, the switch 26 and the switch 27, respectively. The output of the clock generator 19 is connected to the sync input of the shift register 2, the data input and control inputs of which are connected to the output of the OR element 23 and directly to the output of the trigger 22, respectively. The second input element 9 And

connected via switch 26 to the output element 24 OR. The synchronization inputs of the generators 15 and 16 single pulses are connected via switch 27 to the output of the first bit of the distributor 20 pulses.

The subtraction counter works as follows.

The clock generator 19 of the synchronization unit 1 generates a sequence of clock pulses of frequency f, of which the n-bit dispenser 20 pulses form n sequences of pulses with a duration of 1 / f, a period of T n / f and shifted relative to each other by a time of 7 1 / f.

From the sequences of pulses 4 i-x of the bits of the distributor 20 pulses, where i l, 2, ... m, and 4m p, element 24 OR forms a sequence of pulses of 1 / f duration, operating at a frequency of / 4. In the decimal counting mode, the switch 26 connects the output of the element 24 OR to the second input of the element 9 I, and in the binary counting mode, the switch 26 connects the second input of the element 9 AND to the zero bus signal of the counter.

In the initial code setting mode in the shift register 2, the switch 27 connects the synchronization inputs of the generators 15 and 16 of single pulses to the zero signal bus of the counter, thereby blocking the information inputs 17 and 18 of the counter. The initial code for the installation of the counter is set using the switch 25 in a binary-decimal or binary code, depending on the counting mode of the decimal or binary, respectively.

The switch 25 in the unit bits of the initial installation code connects the output of the corresponding bit of the distributor 20 pulses to the inputs of the IlTOi element 23, the output of which generates the serial code of the initial installation of the counter. In the decimal counting mode, the initial installation code is specified as 1-p, tetrads, where n-, r / 4, each of which contains four binary bits and encodes decimal numbers from 8-4-2-1 in binary code About up to 9 according to the table.

In binary counting mode, the initial setup code is specified as an h-bit binary code.

Thus, at the output of the OR element 23, a serial binary-decimal or binary code of the initial installation of the counter is generated. Write the initial installation code

The shift register 2 is implemented using a switch 28, made, for example, in the form of a push-button switch, which starts the generator 21 of single pulses. The output pulse of the single-pulse generator 21 sets the trigger 22 to the time of the n cycles, after which the trigger 22 is reset to the zero state by the pulse of the nth output

pulse distributor. At the direct output of the trigger 22, a single signal of duration n steps is generated, which is fed to the control input of the shift register 2.

the clock pulse generator 19 clock pulses in the shift register 2 is recorded the serial code of the initial installation of the counter, which comes from the output element

23 OR to the input of the register data input 2. shear. The latter contains h-2 bits and is supplemented to the i-bits with delay elements 4 and 5 per clock. After recording, the code for the initial installation of the counter springs dynamically in the code circulation circuit formed by the serial connection of the shift register 2, the binary subtractor 3, elements 4 and

5 delays, elements 7 and 8 AND, which are opened by a single signal acting at the output of element 13 NOT.

Consider the operation of the counter for decoding in the decimal mode, in which the inputs C11 of the generators 15 and 16 of the single pulses go through the switch 27 to the sequence of pulses of the first discharge distribution (20 and 5 pulses). Subtracting the initial pulses of the 5 operating on the information inputs 17 and 18, the counter for subtraction is as follows.

Suppose that in the junior tetrad of the binary-decimal code for the initial installation of the counter, code 1001 (nine) J was recorded and two informational inputs 17 and 18 simultaneously received two pulse signals, the frequency of which should be less than f / n. In this case, the generators of 15 and 16 single pulses simultaneously generate single pulses that coincide with the pulses of the first and distributor 20 pulses and are active during the shift from the register output. 2 shifts of the low order of the lower tetrad of the code for the initial installation of the counter. In the first cycle during the operation of the pulses at the outputs of the generators 15 and 16 single impulses, at the output of the EXCLUSIVE OR 4 element a zero signal is generated, and at the output of element 10 I there is a pulse signal which through element 12 OR enters the input of element 6 of the delay per cycle . Zero signals at the outputs of element 6 hold the element EXCLUSIVE OR 14 for-40, occur when the code of the tetrade 000 (one) arrives from the output of the shift register 2 to the input of the decremented binary subtractor 3, and the information is received simultaneously at the information inputs 17 and 18 of the counter. pulsating signals, which cause the formation of the element 10 AND of the pulse signal during the shift from the output of the register 2 to the shift of the first digit of the lower tetrad. The pulse signal from the output of element 10 I through element 12 ШП1, element 6 of delay and element 1 1 ШШ is fed to the input of the readable binary subtractor 3, and during the shift of the second bit of the low tetrad code from the code of the shift register 2 - to the input binary reader 3. In the recVI

The output of element 11 OR is zero during the shift from the output of register 2 to shift the single signal of the first discharge of the lower tetrad of the code for the initial installation of counter 45 which passes without changing the binary reader 3, and through elements 4 and 5 of the delay, elements 7 and 8 AND are written in register 2 shift.

In the second cycle, at the output of the element-50 and 6-delay, a single signal is formed, which through element 11 OR goes to the input of the subtracted binary subtractor 3, to the input at which time at the time 55 from the output of the shift register 2 the zero signal of the second tetrad shifts initial vc0 code

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Counter settings. At the outputs of the difference and loan binary viitatel 3 a) Ormir; Lots single signals. A single signal through elements 12 Р1ЛИ, element 6. delays and element I1 OR in the next cycle enters the input of a deductible binary subtractor 3, which produces a sequential binary subtraction of the loan signal from the following bits of the lower tetrad of the initial setting of the counter shifted from register output ;; shear. The signals of the difference from the output of the difference of the binary subtractor through delay elements 4 and 5 and elements 7 and 8 AND come on. information input register 2 shift. As a result, in the Junior Tetrad, the initial setup code 1001 (nine) is changed to the code 01J1 (seven) j, which corresponds to the subtraction of two pulses acting on the information inputs 17 and fS of the counter.

If, after the clock cycles, the information inputs 17 and 18 of the counter again receive pulse signals, then the current code 01P (seven) in the lower tetrad, shifted from the output of the shift register 2, is changed to code 0101 (five) in the same way as before. described earlier.

The subtraction counter works in the same way until the difference between the binary subtractor 3 difference and the fourth bit of the notebook is generated from the output of the shift register 2 for the fourth bit of the notebook and a single signal

In this case, this is the result of binary subtraction, which is sequentially performed in time by binary subtractor 3, and the aforementioned code 1111 is formed at its difference output. In this case, during the shift of the fourth bit of the lower tetrad from the output of the shift register 2 at the output of element 24 OR block 1 synchronization is formed of a pulse signal, which through the switch 26 is fed to the second input element 9 I.

Since the output of the difference between the binary subtractor 3 at this time is a single signal of the fourth bit of the forbidden code 1111, then the output of element 9 I generates a pulse signal, which through element 13 does NOT block elements 7 and 8 AND, prohibiting the transmission of the single signal of the second bit yes of the forbidden code of the lower tetrad from the output of the 4th delay element to the information input of the shift register 2 and the single signal of the third discharge of the forbidden code of the lower tetrad from the output of the 5th element to the input of the 4th delay element. As a result Into the shift register 2, it is recorded in the lower tetrad instead of the forbidden code 1111, the current result code IOOI (nine). As the Loriation process uses the binary subtractor 3 of the forbidden code 1111, a loan signal is generated from the fourth bit of the lower tetrad, which through item 12 l fflH, delay element 6 and element 11 OR are fed to the input of the readable binary subtractor 3 during the shift from the output of the shift register 2 of the first discharge of the second tetrad of the code of the initial installation of the counter, then the binary subtractor 3 reduces the initial installation code ki counter on one unit.

Further calculations in all tetrads of the binary-decimal code shifted from the output of the shift register 2 are not analyzed in the same way in the case of simultaneous arrival of information signals 17 and 18 of the pulse signals.

If the pulse signals to the information inputs 17 and 18 are received successively in time or only to one of the information inputs 17 or 18 of the counter, then element 10 I is blocked by a zero output signal, for example, a generator 15 single

pulses, and at the output of the EXCLUSIVE OR 14 element, an impulse output signal is generated, for example, a generator of 16 single pulses. The pulse signal from the output of the EXCLUSIVE OR 14 element is fed through element 1 1 of the ICh-G to the input of the subtractive binary subtractor 3 during the shift from the output of the first digit of the first digit of the lower tetrad of the current binary-decimal code. The binary subtracter 3 decreases the current low tetrade code by one low-order unit, and the result of the subtraction is written through delay elements 4 and 5 and elements 7 and 8 to the shift register 2.

Further calculations are performed by a counter for subtracting in the same way until the end of the pulse train at the information inputs 17 and 18 of the counter.

In this case, at the outputs of the generators 15 and 16 of single pulses, zero signals are generated, which support a zero signal at the input of the subtracted binary subtractor 3. The binary-decimal code of the result of the subtraction from the initial installation code of the counter of two sequences of pulses is recorded dynamically in the code circulation circuit through the shift register 2, the binary subtractor 3, delay elements 4 and 5, and elements 7 and 8 AND, in the binary counting mode using k6 of sync block 26 of synchronization block 1, element 9 AND is blocked, which through element 13 does NOT support elements 7 and 8 And in the open state. As a result, the binary code of the subtraction result from the output of the binary subtractor 3 is written without Changes to register 2 shift through delay elements 4 and 5 and elements 7 and 8 I.

Claims (1)

Invention Formula A subtraction counter containing the shift register, the binary subtractor, the first, second and third delay elements, the first, second, third and fourth AND elements, the first OR element, the NOT element, and a synchronization unit containing a clock generator, pulse distributor, single pulse generator , trigger, two elements OR, and four switches, the output of the clock pulse generator is connected to the clock inputs; the shift register and pulse distributor, the outputs of which bits, where n is the number of bits of the shift register, are connected via the first switch to the inputs of the first OR element of the synchronization unit whose output is connected to the input of the data of the shift register, the output of the n-th bit Yes, the pulse distributor is connected to the zero input of the trigger and to the synchronization input of the generator of single pulses of the synchronization unit, the input of which is connected through the second switch to the zero signal bus of the counter5 generator output one full-time pulses of the synchronization unit are connected to a single trigger input, the direct output of which is connected to the control input of the shift register, outputs 4 ix of the pulse distributor 5 where i 1,2 ,,, m, and 4m - n, are connected to the inputs of the second OR element synchronization, the output of which through the third switch is connected to the first input of the first iBoro element I, the output of the first discharge of the pulse distributor is connected to the information input of the fourth switch of the synchronization unit, the output of the shift register is connected to the input of the decremented binary Reading 5 information input shift register - with the output of the second element And, the first input of which is connected through the first delay element to the output of the third element And, the output of the binary subtractor difference is connected to the second input of the first element And, and through the second delay element - with the first input of the third element AND, the second input of which is combined with the second input of the second element AND and connected through the element NOT to the output of the first element AND, the input of the readable binary subtractor is connected to the output of the first element OR of the counter, the new input of which is connected with the output of the third delay element differs in that, in order to expand the functionality by simultaneous counting through two Channels, in 5, the second and third single pulse generators are entered, the EXCLUSIVE OR element and the second OR element, the binary subtractor loan output is connected to the first input of the second OR element of the counter, the output of which is connected to the third OR element is connected to output element EXCLUSIVE 1 OR, 5 the first entrance of which is combined with the first one; the input of the fourth element None is connected to the output of the second generator of single pulses, the output of the third generator of single pulses is connected to the second inputs of the EXCLUSIVE OR element and the fourth AND element, whose output is connected to the second input of the second OR element; ka, the fourth switch of the synchronization unit is connected with the synchronization inputs of the second and third generators of single pulses, the control inputs of which are respectively the first and second information inputs of the counter. FI.2