SU1624699A1 - Residue system code to positional code converter - Google Patents

Abstract

The invention relates to computing and is intended to convert a code from a system of residual classes into a position code. The purpose of the invention is to simplify the converter. The code converter of the residual classes system to the position code contains four shift registers 1-4, two subtractors 8 and 9, three adders 5-7, a switch U of the base of the residual classes system, switch 11, synchronization unit 12, code comparison circuit 13, two triggers 14 and 15, the three elements And 17-19, the element EXCLUSIVE IPI 16, two elements 20 and 21 of the delay. 4 il.

Description

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The invention relates to computing, is intended to convert a code from a system of residual classes to a position code, and can be used in digital automation and telemechanics.

The purpose of the invention is to simplify the converter.

FIG. 1 shows a block diagram of the converter of the code of the system of residual classes into a position code; figure 2 - block diagram of the synchronization unit; FIG. 3 is a comparison chart; figure 4 is a timing diagram of the synchronizing signals.

The code converter of the residual classes system to the position code contains shift registers 1-4, adders 5-7, subtractors 8 and 9, switch 10 of the residual classes system base, switch 11, synchronization unit 12, code comparison circuit 13, triggers 14 and 15, element EXCLUSIVE OR 16, elements 17-17, elements 20 and 21 of the delay, a group of inputs 22 specifying the range of representation of numbers, two groups of information inputs 23 and 24 and an input 25 of starting the converter. Synchronization unit 12 (Fig. 2) contains a pulse generator 26, a single pulse generator 27, a frequency divider 28, a trigger 29, an AND element 30 and outputs 31-34 of the synchronization unit 12, the direct output of the pulse generator 26 connected to the first input of the And element 30, the output of which is connected to the input of the frequency divider 28, the inverse output of the pulse generator 26 is connected to the clock input of the single pulse generator 27, the control input of which is connected to the converter start input 25, the output of the single pulse generator 27 is connected to the input Trigger unit 29, the direct output of which is connected to the second input of the element 30, the output of the frequency divider 28 is connected to the installation input of the on the trigger 29, the outputs 31, 32.33 and 34 are the first, second, third and fourth outputs synchronization unit 12 and connected respectively to the output of the generator 27 single pulses, with the direct output of the trigger 29, the output of the element 1/1 30 and the output of the frequency divider 28.

The code comparison circuit 13 (FIG. 3) contains bitwise comparison nodes, each of which contains an AND-OR-NO 35 element and an NOT 36 element, with the first inputs of the first and second input groups of the AND-OR 35 element in odd bits. dahs are connected directly, and in even bits, via the NOT 36 element with information inputs 24, the second input of the second group of inputs and the first input of the third group of inputs of the AND-OR-NOT 35 element at odd bits are connected through the NOT 36 element, and in even numbers

bits - directly with information inputs 23, the second inputs of the first and third groups of inputs of the AND-OR-NOT element 35 of all bits, except the first, are connected to the outputs of the AND-OR-NOT 35 elements

of the previous bits, the second inputs of the first and third groups of inputs of the first-bit AND-OR-NO element 35 are connected to the input of the logic zero of the converter, the output of the higher-order AND-OR-NO element 35 is connected to the output 37 of the code comparison circuit 13. The timing diagram at the outputs of synchronization unit 12 (FIG. 4) is composed for positive polarity pulses, with a divider 28 dividing ratio of 2 p 8, i.e. with n 4

The code converter of the system of residual classes to the position code (FIG. 1) works as follows.

In the initial state, the triggers are 14, 15 and

the trigger 29 of the synchronization unit 12 is in the zero state in which they are set as a result of the previous conversion cycle.

Binary input is applied to group 22.

the code of the number representation is Pi P2, where the bases of the system of residual classes Pi 6N-1 and Pa 6N + 1; N 21, 1 0, 1, 2, 3, .... - natural number of numbers. Using switch 10, the base of the residual class system is defined.

Shift register 1 contains 2p bits, while shift registers 2 and 3 contain n-bits, where n is the number of bits to represent residues a 1 and 2 2 at the bases of Pi and P2

residual class systems. Shift register 4 contains m bits, where ch n-3. Parallel n-bit codes of residues a and O.1 are respectively supplied to groups 23 and 24 of information inputs.

converter

The converter is started by supplying a signal 1 to the converter start input 25, which starts the generator 27 of single pulses of block 12

sync. The start signal generator 27 single pulses produces a single pulse in the pause between the clock pulses generated by the generator 26 pulses. Output pulse

5 generator 27 single pulses set. fills the trigger 29 into one state and goes from the output 31 of the synchronization unit 12 to the write enable inputs of registers 1, 2, 3 and 4, as well as

inputs of elements 18 and 19. By this signal, the initial information in the form of parallel binary codes is entered into the shift registers 1, 2 and 3, the shift register 4 is set to the zero state, since its data input inputs are connected to the input O, and the flip-flops 14 and 15 are set to the states defining the mode of operation of the converter.

Parallel n-bit binary codes of residues a-i and a-i are read from the information inputs 23 and 24 of the converter, respectively, and the generator single pulse of the synchronization unit 12 is written to the shift registers 2 and 3, respectively. A parallel 2n-bit binary code of the number representation range is read from a group of inputs 22 specifying the number range representation and is written to the shift register 1 by the pulse of the single-pulse generator 27 of the synchronization unit 12.

The code comparison circuit 13 compares two n-bit parallel binary residual codes acting respectively on information inputs 23 and 24 of the converter and generates a signal 1 at .a.1 a 1 In the case of the output of the code comparison circuit 13, the O signal acts.

If a 2 o. 1, the signal 1 at the output of the code comparison circuit 13 opens an element 18, through which the pulse of the generator 27 of single pulses of the synchronization unit 12 passes and sets the trigger 14 to one state.

In the case of cc.2a, the zero signal at the output of the code comparison circuit 13 blocks the element AND 18 and the trigger 14 saves the zero state.

The EXCLUSIVE OR 16 element compares the lower bits of the binary codes of residuals cn and a2 acting on the first information inputs 23 and 24 of the converter. When various signals act in the lower bits of the binary residual codes (combinations of the lower bits 01 or 10), the output of the EXCLUSIVE OR 16 element produces a signal 1, which opens the element AND 19. The output pulse of the single-pulse generator 27 of the synchronization unit 12 passes through element And 19 and sets the trigger 15 in one state.

 In the case of the combination of the lower-order codes of the residues ai and ag 00 and 11, at the output of the EXCLUSIVE OR 16 element, a signal O is generated, which blocks AND 19 and the trigger 15 retains the zero state.

After the trigger 29 of the synchronization unit 12 is set to one, the clock pulses generated by the pulse generator 26 are fed through element 5 and 30 to the output 33 of the synchronization unit 12 and then to the shift enable inputs of the registers 1, 2, 3 and 4 of the shift.

Under the action of the clock pulses of the generator 26 of the pulses of the synchronization unit 12, the binary codes of the residuals a and ai shift, starting with the least significant bits, with the outputs of the shift registers 2 and 3, respectively. A serial binary code is generated at the output of the adder 7.

5 sums of residues а 1 Л-ai, and at the output of the reader 8 - differences of residues ai - а. A negative difference is generated at the output of the subtractor 8 in the additional code. Binary code residual with

0 output subtraction 8 received on the information input of the register 4 shift and under the action of the clock pulses of the generator, 26 pulses of the synchronization unit 12 after one, two m cycles begins

5 shift accordingly from the outputs of the first, second, ..., t-th bits of the register 4 shift. Since the delay of a sequential code by one clock cycle is equivalent to multiplying by two, then at the outputs of the first, second, ..., m-th bits of the shift register 4, respectively, sequential binary codes of values are formed

2 ("2-cn), 2 2 (0: 2-a i) 2m (" 2-ai)

j- One of these values is selected using the switch 10 of the base of the system of residual classes. Suppose that the base of the system of residual classes Р2 is 6N + 1, where N is 2K. t, then the output to the + 1 th digit of the shift register 4 through the switch 10 is connected to the inputs of the delay element 21 and the adder 6. Consequently, the output of the switch 10 is formed in series

5, the binary code of the value of 2st (), which is delayed by a cycle by the delay element 21, which is equivalent to multiplying this value by two. Thus, at the output of the element 21 delay

0 serial binary code valid

2 (# 2 - O. i), which is summed, starting with the least significant bits, in adder 6 with consecutive binary

by a code of 2 + (ai - a), formed at the output of the switch 10 of the base of the system of residual classes. The output of the adder -6 is a serial binary value code

& -2k (a2 O. t), which is subtracted by the reader 9 from the sequential binary code of the sum of residues a- + 2, acting at the output of the adder 7. At the output of the subtractor 9 successively in time, starting with the least significant bit, a sequential binary code

the values ("1 H-a2) - 6-2k (a2-o: i), which goes to one of the inputs of the adder 5, the flow of information to another input of which depends on the state of the switch 11. If the trigger 15 is in one state , the switch 11 connects the output of the shift register 1 to the input of the adder 5. If the trigger 15 maintains the zero state, then the output of the delay element 20 is connected to the input of the adder 5. Element And 17 blocks the input of delay element 20 if trigger 14 is in the zero state, or connects the output of shift register 1 to the input of delay element 20 when trigger 14 is in the unit state.

After starting the converter, the binary code of the PV P2 value is shifted under the action of the clock pulses of the generator 26 of the pulses of the synchronization unit 12 from the shift register 1, and, starting with the lower bit, is fed through the switch 11 to the input of the adder 5 in the case of a single trigger state 15. In In this case, the output of the adder 5 generates a serial binary code of the value

Pr P2 + (ai + a2) -6-2k (a2-ai), which is equal to twice the value of the converted number.

When the trigger 15 is in the zero state, and the trigger 14 is in the single state, the binary code Pi P2 is shifted from the shift register 1 through the And 17 element, the delay element 20 per clock and the switch 11 to the input of the adder 5. The delay element 20 the tact implements the operation of multiplying the PrgPa value by two consecutive binary codes. In this case, the output of the adder 5 generates a serial binary code of the value

2Pr P2 + (ai + a2) -6-2k (a2-ai) 3, which is equal to twice the value of the converted number.

In the case when the triggers 14 and 15 retain zero states, the AND element 17 is closed by the direct output signal of the trigger 14 and the output of the switch 11 is the zero binary code. In this case, the binary value code

(ai-ct2) -6-2k (a2-ai)

formed at the output of the subtractor 9 and equal to twice the value of the converted number, passes through the adder 5 without change. Serial binary

The double value code of the converted number from the output of the adder 5 in 2p clock cycles is written to the shift register 1 under the action of clock pulses from the output of the And 30 element of the synchronization unit 12.

After 2p clocks after starting the converter, a pulse is generated at the output of the frequency divider 28, which sets the trigger 29 of the synchronization unit 12

(Fig. 2) to the zero state. The pulse generated at the output of the frequency divider 28 arrives at the output 34 of the synchronization unit 12 and sets the triggers 14 and 15 to zero states, the trigger 29 of the unit 12

synchronization in the zero state generates a signal O on the direct output, which is output to the output 32 of the synchronization unit 12 and stops the computation in the subtractors 8 and 9. The zero signal is direct

the output of the trigger 29 also blocks the element AND 30 and at the output 33 of the synchronization unit 12 a zero signal is generated, which terminates the process of shifting information in the registers 1, 2, 3 and 4 of the shift.

Thus, after 2p clocks, after starting the converter, the binary code of the transformed number having residues and a 2 through

bases PI 6-2K-1 and P2 6-2K + 1, respectively. The binary code of the converted number can be read from the outputs of the bits of the shift register 1 from the second bit to 2 n-th in the form of a parallel binary code.

The code comparison circuit 13 (FIG. 3) works as follows. The inputs 23 and 24 are received, respectively, parallel n-bit codes of residues a 1 and a.i,

5 First, starting from the most significant bit, the combination of codes in the i-th bit is 11 0, and 2 1 forms at the output of the AND-OR-NOT 35 element of even-digit signal 1, and at the output of the AND-OR-NOT element 35

0 odd bit - signal O. This signal with any other combination of codes in the higher bits sequentially passes through the elements AND-OR-NOT 35 to the output 37 of the circuit 13 of the code comparison in

5 as a signal 1. For example, let's say in n-1 bit, the first acts, starting with the highest bit, combining the codes a i (n -1) 0, "2 (n -1) 1. In this case, at the output of the element AND-OR-NOT 35 (p-1) -th

a bit (odd), a signal O is generated, which blocks the first and third groups of inputs of an AND-OR-NOT element 35 of the nth digit, the second group of inputs of which is blocked in the case of any combination of codes in the nth bit, except for a combination of d2 ( p) 0, and 1 (p) 1. Consequently, at the output of the n-th bit (even) element AND-OR-NO 35, a signal 1 is generated, which is output to the output 37 of the code comparison circuit 13 as a signal of the comparison result for the case a z cc 1.

If in all categories of residues a. and a.2 there is no combination of codes а 1 () 0, а2 (i) 1, then in even bits at the outputs of the AND-OR-HE elements 35, the signal O acts, and in odd bits - 1. At the output of the n-th the (even) bit of the AND-OR-NOT 35 element, the signal O, which arrives at the output 37 of the code comparison circuit 13, acts.

Claims (1)

Claim code converter of a system of residual classes into a position code containing four shift registers, three adders, two subtractors, a switch, a switch of a base of a system of residual classes, a synchronization unit, a code comparison circuit, two triggers, an element EXCLUSIVE OR, three elements AND and two delay elements, the recording resolution inputs of the first to fourth shift registers are connected to the first output of the synchronization unit, the second output of which is connected to the resolution input of the first subtractor, the third in the synchronization unit's stroke is connected to the shift resolution inputs of the first to fourth shift registers, the group of inputs for specifying the representation range of the converter numbers is connected respectively to the input data input group of the first shift register, whose information input is connected to the output of the first adder, the output of the first shift register is connected a group of input inputs is given with the first input of the first element I and with the first information input of the switch, the second information input of which is connected to the output of the delay element s of the second shift register is combined with the first group of information inputs code comparing circuit and is a first group of information inputs the converter, the input data input group of the third shift register is combined with the second group of information inputs of the code comparison circuit and is the second group of information inputs of the converter; the outputs of the second and third shift registers are connected respectively to the inputs of the read and decrement first subtractor; the outputs of the bits of the fourth shift register are connected in accordance with the inputs of the switch of the base system of the residual classes, the output of which is connected to the input of the first term of the second adder and the input of the second delay element, the output of which is connected to the input of the second term of the second adder, the direct output of the first trigger is connected to the second input of the first element I, the output of which is connected to the input of the first delay element, the direct output of the second trigger is connected to the control input of the switch, the output of which is connected to the input of the first term of the first adder, the installation inputs in 1 of the first and second triggers are connected respectively to the outputs of the second and third elements And, the first inputs of which are connected to the first the output output of the synchronization unit, the start input is connected to the start input of the converter, the fourth output of the synchronization unit and is connected to the installation inputs of the first and second triggers the output of the code comparison circuit is connected to the second input of the second element And the second input of the third element is And is connected to the output of the element EXCLUSIVE OR, the first and second inputs of which are connected respectively to the first inputs of the first and second groups of information inputs of the converter, characterized in that, in order to simplify the converter, the inputs of the subtracted and decremented second subtractor are connected respectively to the outputs of the second and third adders, the information input of the fourth shift register is connected to the output of the first subtractor, the input of the second term of the first adder is connected to the output of the second subtractor, the resolution input of which is connected to the second output of the synchronization unit, the inputs of the first and the second term of the third adder is connected respectively to the outputs of the second and third shift registers. 23 (f) Fig.Z gi2b 7m GOYA P tkd -I from „JlJlJTJTJTJn FIG A