SU1378026A1 - Generator of pseudorandom frequencies - Google Patents

Abstract

The invention relates to a pulse technique and serves to expand the functionality of the device. For this, a device containing a binary pseudo-random sequence generator 14, entered registers 8-10, correction blocks 1 and 2, character count blocks 6 and 7, sum count block 3, delay elements 4 and 5, single pulse generator 17, OR element 16 and the element HE 18. Due to this, it is possible to control the duration of a series of like single and zero characters. In addition, the current digital digit of characters, i.e. the formation of pseudo-random sequences with given statistical parameters. In the description, examples of the implementation of blocks 6 and 7 of the character count, block 3 of the sum amount and blocks 1 and 2 of the correction are given. 4 з.п, ф-л, 5 Il. with: (L

Description

Phys, G

The invention relates to a pulsed technique and can be used in radio engineering and computer technology.

. The aim of the invention is to extend the functionality of a pseudo-random sequence generator by allowing the duration of a series of like symbols to be controlled.

Figure 1 presents the structural diagram of the generator of pseudo-random sequences; figure 2 - block diagram of the characters; FIG. 3 is a schematic block diagram of the summs block in FIG. 4 is a diagram of the second correction block; FIG. 3 is a diagram of the first correction block.

The pseudorandom sequence generator (Fig. 1) contains the first and second correction blocks 1.2, the sum counting block 3, the first and second delay elements 4.5, the first and second counting blocks 6.7 characters, the first - third registers 8 -10, first - third groups of information buses 11-13, binary pseudo-random sequence generator 14, bus 1 Start, element OR 16, generator of 17 single pulses, element NOT 18, third delay element 19, bus 20 clock pulses connected to the input of the third the delay element 19 and the synchronization input of the generator 14 binary pseudo-random sequence, the output of which is connected to the input of the element HE 18, with the fifth input of the second block 7 of the characters and the first input of the second block 2 of the correction, the output of which is connected to the first input of the first block of the correction 1 and with the second input of the block 3 of the account amounts, the first and second outputs of which are connected to the second and third inputs, respectively, of the first correction block 1, the fourth input of which is connected to the output of the first delay element 4, whose input is connected to the second input of the second block 2

correction, with the output of the second delay element 5 and with the third input of the sum account block 3, the first input of which is connected to the control input of the first register 8, with the first input of the first block of 6 character counts, with the control input of the second register 9, with the installation input generator 14 binary pseudo-random sequence,

with

0

five

0 5 0 5 0 0

Start bus, with the control input of the third register 10 and the first input of the second character counting unit 7, the output of which is connected to the second input of the OR element 16, the fourth input of the second correction unit 2 and the second input of the first character block whose output is connected to the third input of the second correction unit 2, with the second input of the second character counting unit 7 and with the first input of the element OR 16, the output of which is connected to the input of the generator 17 of single pulses, the output of which is connected to the third input of the second character counting unit 7 and with the third Odom first block 6 characters account, the fourth input of which is connected to the input of the second delay element 3, with the output of the third delay element 19 and to fourth input of the second unit 7 characters account. The output of the element HE 18 is connected to the fifth input of the first block of the 6 character counting. The outputs of the first 8, second 9 and third 10 registers are connected to the corresponding information inputs of the sum counting unit 3, the first 6 and second 7 digit counting units, respectively. The inputs of the first 8, second 9 and third 10 registers are connected to information buses 11-13, respectively.

Blocks 6.7 characters (Fig.2) contain the counter iZI pulses, the output of the overflow of which is connected to the input of the element HE 22, the output of which is connected to the first input of the element AND 23, the second input of which is connected to the output of the first element OR 24, the second element OR 25, the output of which is connected to the synchronization input of the pulse counter 21, the output of which is the output of blocks of 6.7 counting characters, the first input of which is connected to the installation input of the pulse counter 21, the information inputs of which are the corresponding information inputs b 6.7 counting characters, the second input of which is connected to the first input of the first element OR 24, the second input of which is connected to the fifth input of blocks of 6.7 counting characters, the third input of which is connected to the first input of the second element OR 25, the second input of which is connected with the fourth entry blocks 6.7 counting characters. The output element And 23 is connected

with the control input of the counter 21 pulses.

The sum counting unit 3 (FIG. 3) contains a reverse shift register 26, the first and second group of outputs of which are connected to the corresponding information inputs of the first 27 and second 28 switches, respectively, the first element is NOT 29, the first element is OR 30, the second element is NOT 31 the second 32 and third 33 elements OR, the delay element 34, the output of which is connected to the first input of the third element OR 33, the output of which is connected to the synchronization input of the reverse shift register 26, the recording resolution of which is connected to the second input of the third element EN 33 and is the first input of block 3 of the sum account, the second input of which is connected to the input of the second element NOT 31 and the first input of the second element OR 32, the output of which is connected to the right shift input of the reversing shift register 26 which is connected to the output of the first element OR 30, the first and second inputs of which are connected respectively to the output of the second element NOT 31 and to the output of the second switch 28, the output of which is connected to the input of the first element NOT 29, the output of which is the second output of the counting unit 3 with The first output of which is connected to the second input of the second element OR 32 and to the output of the first switch 27, the control inputs of which and the control inputs of the second switch 28 are the corresponding information inputs of the sum counting unit 3, the third input of which is connected to the input of the element 34 delays.

The second block 2 correction (figure 4)

contains a D-trigger 35 and successively, consistently connected first 36 and second 37 elements EXCLUSIVE OR. The output of the D-flip-flop 35 is the output of the second correction unit 2, the first input of which is connected to the first input of the first EXCLUSIVE OR 36 element, the second input of which is connected to the third input of the second correction unit 2, the second input of which is connected to the synchronization input of the D-trigger 35 The fourth input of the second correction unit 2 is connected to the second input.

with fg 15 20 25 DA, Q 45

50

55

house of the second element EXCLUSIVE OR 37.

The first correction block 1 (FIG. 5) contains a D-flip-flop 38, the information input of which is connected to the output of an AND 39 element, the first input of which is connected to the output of an OR 40 element. The output of the D-flip-flop 38 is the output of the first correction 1 block, the first input which is connected to the first input of the element OR 40, the second input of which is connected to the second input of the first correction unit 1, the third input

 f

which is connected to the second input element And 39. The fourth input of the first correction unit 1 is connected to the synchronization input of the D-flip-flop 38.

The generator of pseudorandom sequences (figure 1) works as follows.

When a positive pulse is applied to bus 15, a binary pseudo-random sequence generator 14 is set to the initial state, information is recorded in the first 8, second 9 and third 10 registers from information buses 11, 12 and 13, respectively, and pulse counters 21 in the first 6 are reset. and the second 7 blocks of counting characters (Fig. 2), the reversing shift register 26 in the counting block 3 (Fig. 3) is set to the write state and to it (in its zero bit, since the reversing shift register 26 is divided into three groups of bits: first n bits, the center zero bit and the second n bits) through the third element OR 33 of the sum counting block 3 is recorded signal 1. When the counters 21 pulses of the first 6 and second 7 count blocks of characters are reset to the zero state, their transfer outputs appear the signal 1, which through the element OR 16 enters (from the output of the second block 7 of the counting of characters) to the input of the generator 17 single pulses. The latter forms a single positive pulse coming through the second element OR 25 of the first block 6 of the character count (figure 2) to the synchronization input of its pulse counter 21. At the same time, the signal from the transfer output of the pulse counter 21 is inverted by the element HE 22 and fed to the input of the element 23, the output of which n is the zero logical signal.

setting the pulse counter 21 to the state of recording information received at its information inputs from condition registers 9, 10, respectively, for blocks of 6.7 symbol counts and recorded by a signal from the generator output 17 of single pulses to their pulse counters 21 pulses.

13780266

fishing The delay element 19 provides a delay of clock pulses at the time of transition processes in the generator 14 g of a binary, randomly random sequence, the signal from the output of which also goes to the first input of the second correction unit 2, i.e. At the entrance of his first element SPLE

Blocks 6 and 7 of the symbol count are provided by the SUPPLIER OR 36, to another input which counts the number of the following categories of symbols (ones and zeros, respectively) and the control signal when the specified number arrives to the device via information buses 12 and 13.

With the delivery of clock pulses to the clock 20 clock pulses at the output of the binary 14 pseudo-random sequence generator, a sequence is generated that arrives through the first element OR 24 and the AND 23 element at the counting resolution input of the pulse counter 21 of the character counting unit 7. Pulse counter 21 operates in the subtraction mode, and when the O signal arrives at its input from the generator 14

from generator 1 output, it restores (by information inputs under the action of the next clock pulse) its initial state. If, in the subtraction mode, the counter 21 counts to zero, then a 1 signal appears at its output, ensuring that initial conditions are written to it, as well as incoming (through the OR 16 element) to the input of the generator 17 single pulses, a pulse from the output which provides the rewriting of information from the register 10. At the same time, the signal 1 from the output of the transfer of the counter 21 pulses of the block 7 of the characters count, i.e. from the output of the latter, is fed to the input of the element OR 24 of the block 6 of character counting and then to the input of its element AND 23, the second input of which contains signal 1, which provides a counting mode in the pulse counter 21, the contents of which are reduced by one for each pulse from the output generator 17 single pulses. The operation of the character counting unit 6 is similar to the operation of the character counting unit 7, but due to the inversion of the signals from the generator 14 output of the binary pseudo-random sequence by the element NOT 18 blocks, 6 characters counting counts the number of additional 1X characters

five

0

five

0

five

It receives a signal from the output of block 6 counting characters. If the signal from the output of block 6 of the character count is zero, then the information on the D input of the D-flip-flop is 35

5 is transmitted unchanged. When a binary pseudo-random sequence appears at the output of the generator 14, an extra single character at the output of the second element is EXCLUSIVE

0 OR 37, a zero signal appears, which is written to the D-flip-flop by a clock pulse. Delay element 3 delays clock pulses for the response time of 6.7 character counting blocks, after which the pulses arrive at the third input of the sum counting unit 3 (FIG. ), providing a count of the current digital sum of a pseudo-random sequence, with single characters through the last OR element 32 supplied to the right shift input of its reverse shift register 26, and the zero characters are inverted by the HE element 31 and given an OR gate 30 to the shift enable input 26 to the left reversible shift register. The clock pulses delayed by the delay element 34 of the sum counting unit 3 by the response time of correction block 2, the single character is shifted left or right in the reverse shift register 26, information from the corresponding output groups of which is fed to the information inputs of the switches 27, 28, to whose address inputs The value of the digital sum comes from the first register of 8 conditions. Upon receipt of a single signal from the outputs of the reverse shift register 26 to one of the inputs, whose address is recorded in register 8 of switch 27 (28), signal 1 appears at the output of the latter, which is fed to the corresponding input of the first correction unit 1 and through the OR element 32 (element OR 30) to the input of the resolution of the shift to the right (left) of the register 26 of the shift of block 3

five

0

7

II h II

one

invoice amount. If 1 appears at the output of switch 27, i.e. at the first output of the sum block 3, it goes to the input of the OR 4 element of the first correction block 1 (figure 5), to another input of which the pseudo-slider sequence is received from the output of the correction block 2. The signal 1 from the output of the element OR 40 is supplied to the first input of the element I 39, the second input of which receives a signal from the second output of the block 3 of the sum account. If 1 appears at the output of the switch 28, then it is inverted by the element NOT 29, providing a signal O at the output of the element 39. The corrected information is recorded by the clock pulse delayed by the delay element 4, at the D-flip-flop 38.

Thus, in the device, the duration of a series of successive sequences of the following single and zero characters is controlled, as well as the control and limitation of the current digital sum of the characters, i.e. the formation of pseudo-random sequences with given statistical parameters.

Claims (5)

1. Pseudo-Random Generator sequences, containing a clock pulse bus, connected to the synchronization input of a binary pseudo-random sequence generator, characterized in that, in order to extend the functionality by enabling the control of the duration of a series of like symbols, the first, second and third registers, the first and second correction blocks are entered into it , the first and second blocks of the counting of characters, the block of the sum, the first, second and third delay elements, the generator of single pulses, the element OR, the element E and tire Start, coupled to the control inputs of the first, second and third registers, to the first inputs of first, second bill symbol blocks to a first input of the bill and to the input for setting the binary pseudo-random sequence generator, whose output is connected to the input element NOT, with the fifth input of the second looped first and second elements eight u 0 50 five 0 five 0 five symbols and with the first input of the second correction block, the output of which is connected to the first input of the first correction block and the second input of the sum account block, the first and second outputs of which are connected respectively to the second and third inputs of the first correction block, the fourth input of which is connected with the output of the first delay element, the input of which is connected to the third input of the sum account block, the output of the second delay element and the second input of the second correction block, the third input of which is connected to the output of the first block account characters, with the first input of the OR element and with the second input of the second character counting block, the output of which is connected to the fourth input of the second correction block, the second input of the first character counting block and the second input of the OR element, whose output is connected to the input of a single pulse generator, the output of which is connected to the third input of the first symbol counting unit and to the third input of the second character counting unit, the fourth input of which is connected to the output of the third delay element, to the input of the second Delay element and to the fourth input th first block of symbols account a fifth input coupled to the output of NOT circuit, a third delay element input coupled to the bus clock, the outputs of the first, second and third registers are connected to the data inputs of the respectively unit bill, the first and second blocks of symbols account. 2. The generator according to claim 1, characterized in that the first correction unit comprises an OR element connected in series, an AND element and D-flip-flop, the output of which is the output of the first correction unit, the first input of which is connected to the first input of the OR element, the second input of which is connected to the second input of the first correction unit, the third input of which is connected to the second input of the And element, the fourth input of the first correction unit connected to the D-flip-flop sync input. 3. The generator according to claim 1, characterized in that the second correction unit comprises successively a COUNTER OR or D trigger, the output of which is the output of the second correction block, the first input of which is connected to the first input of the first element EXCLUSIVE OR, the second input of which is connected to the third input of the second correction unit, the second input of which is connected to the synchronization input of the D-flip-flop, the fourth input of the second correction block is connected to the second input of the second element EXCLUSIVE OR, 4. The generator according to claim 1, which is duplicated by the fact that the sum counting block contains a reverse shift register, the first and second groups of outputs of which are connected to the corresponding information inputs of the first and second switches, respectively, the first element is NOT, the first, second and the third OR element, the second NOT element, the delay element whose output is connected to the first input of the third OR element, the output of which is connected to the synchronous input of the reverse shift register, the recording resolution of which is connected to the second input of the third el OR is the first input of the sum counting block, the second input of which is connected to the input of the second element NOT and the first input of the second OR element, the output of which is connected to the right shift input of the reverse shift register, the left shift input of which is connected to the output of the first OR element, and the second inputs of which are connected respectively with the release of the second element and not with you 5 Q five 0 the second switch, the output of which is connected to the input of the first element NOT, the output of which is the second output of the sum counting unit, the first output of which is connected to the second input of the second OR element and the output of the first switch, the control inputs of which and the control inputs of the second switch are corresponding information inputs of the counting block, the third input of which is connected to the input of the delay element. 5. The generator according to claim 1, wherein; in that the symbol counting block contains a pulse counter, the overflow output of which is connected to the input of the NOT element, the output of which is connected to the first input of the AND element, the second input to cheaply connected to the output of the first OR element, the second OR element, whose output is connected to the synchronization input of the counter pulses, the output of which is the output of the symbol counting block, the first input of which is connected to the input of the pulse counter installation, whose information inputs are the corresponding information inputs of the counting block C oxen, the second input of which is connected to the first input of the first OR element, the second input of which is connected to the fifth input of the character counting block, the third input of which is connected to the first input of the second OR element, the second input of which is connected to the fourth input of the character counting block, AND output connected to the control input of a pulse counter. fpue. 2 (pus. 3 .J J 9Ji / 5, t FIG. five J7 35 38 D