SU868975A1 - Pulse generator - Google Patents

Description

The invention relates to a pulse technique and can be used to generate pulse signals modulated at a repetition rate. $

A generator is known that contains two counters, the outputs of which are connected to a bitwise comparison unit, and the outputs of the pulse generators are connected to the inputs of the counters (1].

The disadvantage of this device is the lack of modulation capabilities for the pulse repetition rate.

The closest technical solution to the proposed is a pulse generator containing two elements 15, which are connected to the inputs of two counters by the outputs, the first inputs of the elements AND are connected to the output of the clock generator, the first input of the first element I is directly, and the second the input of the second element And through the inverter is connected to the output of the block bitwise comparison [2].

The disadvantage of this device is the limited functionality of the pulse generator.

The purpose of the invention is to expand the functionality of the device. thirty

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This goal is achieved by the fact that in the pulse generator containing the first and second elements And, the first inputs of which are connected to the output of the clock generator, the second input of the first element And through the element NOT, and the second input of the second directly connected to the output of the bitwise comparison unit, bit whose inputs are connected to outputs of the bit summiruyu-, present a pulse counter, a first input coupled to an output of the first aND gate and the second input - to the output ⁴ of the second aND gate and the input of the subtracter counter impu There is a ring shift register and a logic switch, the first and second outputs of which are connected respectively to the first and second inputs of the one-bit comparison unit, the first input to the control signal bus, the second input to the output of the detracting counter pulses, the third input to the output ring shift register, the input of which is connected to the output of the second element I.

FIG. 1 shows a block diagram of a pulse generator, 'in FIG. 2 3

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diagrams explaining the operation of the device.

The device contains a generator of 1 clock pulses, the output of which is connected to the first inputs of the first 2 and second 3. Elements I. The output of the first element I 2 is connected to the first input of a summing counter 4 pulses, the output of the second element I 3 is connected to the second input of a summing counter 4 pulses with inputs of the subtractive counter 5 pulses and a ring shift register 6, the outputs of which are respectively connected to the second and third inputs of the logic switch 7 connected by the first input to the control signal bus.

The device also contains a unit 8 bitwise comparison, the bit inputs of which are connected to the discharge outputs of the summing counter 4 pulses, the first and second inputs to the first and second outputs of the logic switch 7, and the output directly from the second input of the second element I 3, and through the element 9 with the second input of the first element And 2.

The device works as follows.

Before the arrival of the first pulse of the generator 1 clock pulses, the counter 4 pulses is set to zero, in all bits of the counter 5 pulses and the high bit of the register b write units.

The device works in two modes. In the first mode, a signal is present on the control signal bus, which corresponds to a logical "O", and in the second mode of operation of the device, there is no signal on the control signal bus, which corresponds to a logical "1".

Consider the first mode of operation of the device. In this case, the register 6 is disconnected from the block 8 by the logical switch 7 and the block 8 is connected to the output of the counter 5. When the generator 1 is turned on, the clock and pulses (Fig. 2) through the AND 2 element arrive at the input of the counter 4. After passing (2 ^m -1 a) pulses all bits of the counter 4 are set to one (where And is the number of bits of the counter 4 pulses). With schetchyka bit output 4 bit information is supplied to the inputs 8 _x n s 4 filled counter pulses at the output of unit 8 is set logic level "1", which opens the second AND gate 3, and the first member 2 and closes through the NOT element 9.

Then, the trailing edge of the first pulse that passed through the element 3, the counter of 4 pulses is reset to zero, and the number recorded in the counter of 5 pulses decreases by one. As a consequence, the output block 8

the logical level “O” is set again. As a result, the output of block 8 (device) forms the first impulse with duration, equal to! Noah period of clock pulses (Fig. 20 ") ·. In the device, the counter 4, elements 2 and 3, block 8 are set to the original state, the number recorded in the counter 5 is reduced by one than before the formation of the first output pulse.

After passing through element 2 ((2 ^nd -2) pulses, the numbers recorded in counters 4 and 5 will become equal, with the result that at the output of block 8 a second pulse is formed, separated from the previous (2 ^m -2) periods of clock pulses. Further processes are repeated similarly at the end of the cycle when the input pulse counter 5 February ¹¹ passes pulses, it is placed back in its original position. Then begins a new forming cycle the output pulse sequence repetition period at which changes in accordance with an arithmetic rogressii.

In the second mode of operation of the device, the counter 5 is switched off by the logical switch 7 from the block 8, the shift register 6 is connected to the block 8.

Before the first pulse of the generator 1, all bits of the register 6 except the high one are set to zero, and the high one to one.

Clock pulses through the element to the input of the counter 4 pulses (Fig. 2 · $). After passing 2 ⁿ -1 pulses, the high bit of counter 4 is set to 'Ί ", and all others will have logical" O ". At the same time, the output of block 8 of the bitwise comparison will set the logical level" 1 ", which opens element 3, and element 2 then the trailing edge of the first pulse transmitted through element 3, the counter 4 is set to zero, and the unit of the high-order discharge of the ring shift register 6 is shifted to the left to the next one with the high-order bit. As a result, the output of block 8 will again be set to logic level “O”, i.e., the back front of the output pulse is formed (FIG. 2b).

In this case, the element 2 is open, the element 3 is closed, the register will record a number 2 times less than before the formation of the first output pulse. After passing through the element 2 (2 ^ -2) impulses, the numbers recorded in counter 4 and register 8 will become equal, as a result of which the output of block 8 again appears logical "O", and a second impulse is formed, separated from the previous one by the interval (2 ^and -2) T _O (T _o - the period of clock pulses).

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Further processes are repeated in the same way. In this case, the interval between the following pulses will be 2 times less than the previous interval (figure 2 g).

After passing the 6 η pulses to the input of the register, it will once again be set to the position when, in all digits except the most significant one, zeros are written and the cycle of formation of the pulse sequence begins. In this case, the pulse repetition period varies according to the law of a geometric progression.

The proposed device generates a sequence of pulses, changing both according to the law of an arithmetic progression, and according to the law of a geometric progression.

Claims (1)

Claim " The pulse generator containing the first and second elements is And, the first inputs of which are connected to the output of the clock pulse generator, the second input of the first element And through the element NOT, and the second input of the second directly connected to the output of the bitwise comparison unit, the bit inputs of which are connected to the digit outputs of the summing pulse counter, the first input of which is connected to the output of the first element G and, and the second input - with the output of the second ^e element And the input of the subtractive impulse counter, characterized in that, in order to extend the functionality, an annular shear '° ^! the register and the logical switch, the first and second outputs of which are connected respectively to the first and second inputs of the bitwise comparison unit, the first input to the control signal bus, the second input to the output of the deductive pulse counter, the third input to the output of the ring shift register, the input which is connected to the output of the second element of I.