SU1045369A1 - Device for pulse delay - Google Patents

Abstract

1. A DEVICE FOR DELAYING PULSES, containing a shift register with parametric delay elements, a group of AND-NOT elements, an OR-NOT element whose output is connected to the synchronization inputs of trigger triggers, the inverse outputs of which are parametric, delay elements, and My outputs are directly connected in bit via the corresponding NAND element to the inputs of the NOR element, the single input of the first and the direct output of the last register trigger are connected respectively to the input and output of the device , characterized in that, in order to increase the reliability of information transfer, a delay element and a pulse subtraction unit are introduced into it, the output of which is connected to the auxiliary input of the OR-NOT element; the first input is combined with the counting inputs of the shift register triggers and the input of the delay element; connected to the second input of the pulse subtraction unit, 2, The device according to claim 1, characterized in that the subtraction unit consists of element 2И-OR, a trigger and the element AND-NOT, the output of the last one is the output of the subtractor, direct in d is connected to the second input of the subtraction unit and the first information input, the input of the 2I-OR element is the first control input, which is connected to the inverse input of the NAND element and the trigger output, the counting input of the last is combined with the output, and the forward output is connected to the second control element 2I-OR, the second information input of which serves as the first S-ey. input block subtraction and t; sd sh about

Description

The invention relates to a pulse technique and can be used in measuring and computing devices. A device for delaying pulses, containing a delay element, trip-bp control, a relief valve, 1-HE elements, a HE element, a two-stroke re: gist, is known. shear l The disadvantage of this device is the relatively low accuracy of restoring the duration of the delayed pulse in the high-frequency region, comparable to the frequency of the clock pulse generator and the pulse-front delay element, and with the differential The closest circuit in the closest technical condition to the proposed one is a device for delaying and dauls, containing a shift register, with parametric elements. delays, the group of AND-NOT elements and the element OR-NOT the output of which is - ; is connected to the synchronizing inputs of the shift register triggers, the inverse outputs of which are via parametric delay elements, and the direct outputs are directly bitwise connected through the corresponding element to the inputs of the OR-NOT element, and the single input: the first and the last output of the lastregister triggers are connected respectively to the input and output of device 2, O, however, the known device is not sufficiently reliable due to the occurrence of failures caused by the competition process during the formation of impulses of the following feedback from the potential differences of the triggers of the switching moment of the latter, The absence of impulse in case of failure causes the register to stop and to exclude the delayed information. The purpose of the invention is to increase the reliability of the transfer of p-i information. The goal is achieved by the fact that the device containing the shift register with parametric delay elements, the group of elements AND-NE element OR-NOT, the output of which is connected to the synchronization inputs of the shift register triggers the inverse outputs through parametric delay elements output directly directly through the bottom is connected via the corresponding AND-NOT element to the inputs of the OR-NOT element, the single input of the first and the direct output of the last trigger of the IHCTpa are connected respectively to the input and output y triplets, additionally introduced a delay element and a block of read pulses 1.sh pulses, the output of which is connected to the additional input of the I element. The first input is combined with the counting inputs of the shift register triggers and the input of the delay element, the output of the last one is connected impulses. Moreover, the subtraction unit consists of the element, the trigger and the NAND element, the output of the latter is the output of the subtraction unit, directly aho, and is connected to the second input of the subtraction unit and the first info-p, / input of the 2I-OR element, the first pack Aulus yuschy aoedinen input thereof with the inverse input of the AND-NOT output of the flip-flop and, counting input of the latter is combined with the output, and a direct output from the second control input of the second information input from, puzhit first input of subtractor blska impulssv. Fig. 1 shows the functional diagram of the device, Fig. 2 shows the operation patterns, which explain the principle of impulse recovery at failures. The device contains a shift register 1 with triggers (.2-1) -) with parametric elements 3-1,) (3-W) delays, elements AND-NOT (, 4-1) i, 4-N), element OR- NOT 5, delay element 6 and impedance subtraction unit 7, consisting of element 2I-OR 8., trigger 9 and element AND-NE, The group 6 of delay can be, for example, a group of series-connected logic elements. The device works (in the absence of failures) as follows. When a device enters a series of latitude, frequency, and number of modulated pulses, they sequentially move in register 1 to the OUTPUT of the device and are formed on the d output of the 2-U flip-flop with a delay, Triggers 2-1 ii 1,2,,, t, i), register 1 is switched when there are potentials of the same name at the inverse output and a single input, as well as a cool potential at the synchronization input of the trigger data, At the moment ne; trigger 2- I switch on its outputs, the potential change occurs simultaneously at the same time due to the transition: x processes caused by the trigger parameters. To do this, the register trigger outputs (tianpHMep ,,, inverse); parametric elements 3-i delays are connected that determine -the transient processes Corresponding flip-flop At the inputs of element 4-i sequentially in time during the switching process of flip-flop 2-1, there are different polarities, then unipolar and again polarity potentials, at the moment of generation of impulses} s one; 1; (/ - example, a logical unit at the output of the element - NOT 4 forms a deterministic pulse, which through the element 5 OR-YA arrives at the synchronization input of the trigger register 1) Following the decline of the pulse generated in this way, the next 2- (f + 1) triggers of register 1, etc. In the process of moving the delayed pulse through register 1, at the output of the OR-NOT 5 element (Fig. 2a), a packet of pulses of the following feedback is formed, due to the switching of the triggers (, 2-1) (2-N), The pulse sequence from the output of the element 5 (.Fig.2a) p It comes to the first, and through the element 6, the delay to the second inputs of the subtraction unit 7. At the output of element b, servo feedback pulses appear with settling for time tr. (FIG. 2b), which you choose is equal to or longer than the clock pulse repetition period. The delay time is mainly determined by the transient time of the parametric element 3-- trigger delay of register 1, which has the longest switching time. At the output of block 7 (FIG. , 2c) pulses (-3, j -2, -1) are missing. The pulses ya of the second input of the unit 7 are 2 pulses behind the pulses at the first input of the subtraction unit 7. The impulse (-3) comes through the second open element 2I-OR 8 to the counting input of the trigger 9 and switches it down with a recession. to zero state. The first input of block 7 of the subtraction is blocked, and (j -2) -th pulse to the counting input of trigger 9 is not received. At this time, a potential is present at the inverted output of trigger -9, the AND – NE element 10 is closed, and the first element 2I -Or 8 is open. The impulse (j -3} through; the second input of block 7 through element 8 enters the counting input of trigger 9 and drops it into one state, while the output of block 7 does not arrive. Pulses (/ -2, jf, j); The next pulses of the first input are crossed out in block 7; they are subtracted pulses (respectively, j -3, 5 -2, j -1,: appearing through delay element 6 at the second input. At the output of block 7, there is a unit potential with no failures in the device , At the time of occurrence of a pulse (jil} from the output of the delayed element b, through the open element 10 enters the output of the block 7. Subtraction. At the output, de block 7 appears zero. The potential affects the additional; the input of the element OR NOT 5, the output of which forms the next 1 K - I 1 st clock pulse trace feedback. After switching (2 - C) –HY of the trigger of register 1 of the forms: pulses are ruled in the usual way (C – P g + €) along the ring of the following inversion; the outputs of the trigger (2–1) (2– (L of the register 1 taking into account the parametric delay elements (3 -1) - (3- N), 4-k, 5 elements, synchronizing inputs of register 1 triggers, Thus, at the time of the missing clock pulse Bc is formed by a delay element 6 and a pulsation block 7. Compare the proposed device with the known. The reliability of the M device for 5; cycles, (j -I, 2, .fi, and) is determined by Q-.n. For reasons of reasoning, the probabilities c,: - C,, are the same, we get Let the failure occur on the K -th cycle, then the probability failure of the known device C {L The known device fails, and the proposed operation continues due to regeneration of the Feedback pulse, and the probability of failure, Q / i of the proposed device, is defined as. Comparing the probabilities of failure of the known Q and the proposed device Q, we get Q.-VQ-I, i.e. The probability of a QJ prototype failure is й times higher than the probability of a Qrt failure of the proposed device, or in other words, the proposed device is H-® times more reliable than the known one. IntroductionIn the proposed device of the delay element and the pulse subtraction unit, the reliability of information transmission is increased tys times by generating an additional clock pulse at the moment of the occurrence of servo feedback pulses, which increases the reliability of information transmission.

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Claims (2)

1. A DEVICE FOR DELAYING PULSES, containing a shift register with parametric elements of the e. Delay, a group of AND-NOT elements, an OR-HE element, the output of which is connected to the 'synchronizing inputs of the shift register triggers, whose inverse outputs are through parametric, delay elements, and direct outputs are directly bitwise connected through the corresponding AND-NOT element to the inputs of the OR-HE element, and the single input of the first and direct output of the last register triggers are connected respectively to the input and output of the device, In that, with the goal of increasing the reliability of information transfer, a delay element and a pulse subtraction unit are introduced into it, the output of which is connected to the additional input of the OR-NOT element, the first input is combined with the counting inputs of the shift register triggers and the input of the delay element, the output of the latter is connected to the second input of the pulse subtraction unit 2, The device according to claim 1, wherein the subtraction unit consists of an AND-OR element, a trigger and an AND-NOT element, the output of the latter is the output of the subtraction unit, the direct input is connected to the second input the subtraction unit and the first information input of the AND-OR element 2, the first control input which is connected to the inverse input of the AND-NOT element and the trigger output, the counting input of the latter is combined with the output, and the direct output is the second control input of the 2-OR element, the second information the input of which serves as the first input of the subtraction unit and pulses. 10 4 5