SU1658391A1 - Serial-to-parallel code converter - Google Patents

Abstract

The invention relates to computing and can be used in data processing systems. The invention provides for the conversion of a CI code (GOST 24152-83) into a parallel code, which allows to expand the range of application of the converter. The converter contains And 1 and 2 elements, trigger 3, shift register 4 , shaper 5 pulses, unit 6 elementwise comparison, the element EXCLUSIVE OR 7, the element OR 8, the elements 9 and 10 of the delay 2 or

Description

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The invention relates to computing and can be used in data processing systems.

The aim of the invention is to expand the field of application of the converter by providing conversion of the KI code.

FIG. 1 shows a functional diagram of the converter; in fig. 2 - time diagrams that show his work.

The converter contains the first and second elements AND 1 and 2, the trigger 3, the shift register 4, the pulse shaper 5, the unit 6 element-by-element comparison, the element EXCLUSIVE OR 7, the element OR 8, the first and second elements 9 and 10 of the delay. FIG. 1, reference numerals 11-13 designate the input and the first and second outputs of the converter, respectively. FIG. 2 corresponding indices denote the following signals: a - signal at input 11, b and c - signals at the first and second output of shaper 5, g and d - signals at the outputs of elements 9 and 10, e and f - signals at the outputs of elements 2 and 1 h) signals at the output of element 8, and signal at the output of trigger 3, k signals at the output of element 7, l signals at the output of 12, m signals at the output of 13.

The code KI is a sequence of sinusoidal signals. In an KI code, a logical unit is transmitted by changing the phase of a sinusoidal signal per l with respect to the previous sinusoidal signal, and logical zero is repeated by repeating the phase of the previous sinusoidal signal.

Register 4 shift can be performed on 13 integrated circuits 564PR1. The information input of the microcircuit is the input of the 4th shift register, the information input of each next microcircuit is connected to the higher-order output of the previous microcircuit, the clock inputs of all the microcircuits are combined and are the control input of the 4th shift. Outputs of bits 3 ... 10, 28 ... 35, 40, .. 47, 53 ... 60, 65 ... 72, 78 ... 85, 90 ... 97 registers 4 shift (in the code The CI in the specified bits is transmitted useful information) are the first output (group, consisting of 56 lines) of the register 4 shift, and the outputs of bits 1,2,11m ... 27, 36 ... 39, 48. ..61 ... 64, 73 ... 77, 86 ... 89, 98 ... 100 shift register 4 - the second output (group, consisting of 44 lines) of shift register 4.

Element-by-element comparison unit 6 is a unit of elements I. Its direct inputs are connected to the outputs.

bits 1, 11, 14, 26. 36 ... 39, 49 ... 51., 61, 62, 64, 74, 76, 86, 88, 89, 100 of the shift register 4 (in the code KI in the specified bits dah, the logical unit is transmitted respectively, and the inverse inputs are transmitted with the outputs of bits 2, 12. 13, 15 ... 25, 27, 48, 52. 73, 75, 77, 87, 98, 99 shift registers 4 (in the CI code logical bits are transmitted at the indicated bits and the first input of block 6, respectively. A high signal level at the output of block 6 corresponds to the presence of high levels of signals at all of its direct inputs and low levels of signals at all

its inverse inputs. A high signal level at the first (second) output of the imaging unit 5 is formed in the presence of a positive (negative) half-wave of a sinusoidal signal at its input. The pulse signal generated at the first output of the imaging unit 5, is fed to the input of the delay element 9 and the second input of the element And 2. The pulse signal generated at the second output of the imaging device

5, is fed to the input element 10 of the delay and the second input of the first element And 1.

The delay time of the signals generated at the outputs of the elements 9 and 10 of the delay (z), is chosen from the condition

Go T T -T1.

where T0 is the minimum allowable pulse duration at the second input of trigger 3; G1 - the minimum allowed duration of the interval between the leading edges of the pulses on the second and first input of the trigger 3;

T - the duration of the half-wave of a sinusoidal signal in the code KI.

Pulse signal generated

at the output of the first delay element 9, enters the first input of the element 2I, the first input of the trigger 3 and the first input of the element 7 EXCLUSIVE OR.

Pulse signal generated

at the output of the element 10 delay, arrives at the first input of the element And 1.

A high signal level at the output of the second (first) element 2 (1) is formed when there are high levels of signals at its inputs. The pulses generated at the outputs of the elements AND 2 and 1, through the element OR 8, are fed to the second input of the trigger 3. the control input of the shift register 4 and the second input of the analysis unit 6.

On the leading edge of the pulse formed at the output of the element OR 8. If a high level of the signal at the output of the trigger 3 is present at the input of the trigger 3, a high (low) signal level is established. The pulse signal generated at the output of the trigger 3, is fed to the first input element EXCLUSIVE OR 7.

A high signal level at the output of the EXCLUSIVE OR element 7 is formed when there is a high signal level at one of its inputs. The pulse signal generated at the output of the EXCLUSIVE OR 7 element is fed to the input of the shift register 4.

On the leading edge of a pulse formed at the output of the element OR 8. in the presence of a high (low) signal level at the input of the shift register 4, the logical unit (logic zero) is written to the low-order bit of the shift register 4, and the information previously recorded in the shift register 4 is shifted .one bit toward the older bit.

When a given code is set at the second output of register 4, a predetermined code is in the interval between adjacent pulses at the output of the element OR 8, a high signal level is formed at the output of block 6. The pulse generated at the output of block 6, is fed to the second output 13.

A parallel digital code formed on the first output of the shift register 14 is fed to the first output 12.

On the leading edge of a pulse formed at the second output 13, a parallel digital code formed at the first output 12, and carrying useful information, is written into the receiving (external) register of the data processing system.

Claims (1)

Claims A serial to parallel converter that contains And elements, a trigger, a shift register whose first outputs are the first output of a converter, differing in that. what. in order to expand the field of application of the converter by providing conversion of the KI code. an element-by-element comparison unit, an EXCLUSIVE OR element, an OR element, delay elements, and a pulse shaper, the first output of which is connected directly to the first the input of the first element And through the first delay element - with the first inputs of the second element AND, the trigger and the element SPEAKER, or the output of which is connected to the information input the shift register, the second outputs of which are connected to the first inputs of the element-by-element comparison unit, the second output of the pulse shaper is connected directly to the second input of the second element And through the second delay element to the second input of the first element And, the outputs of the first and second elements And are connected to the same inputs of the element OR, the output of which is connected to the second trigger input, to the control input of the shift register and to the second input of the element-by-element comparison unit, the output of which is the second output of the converter l, the trigger output is connected to the second input element EXCLUSIVE OR, the input of the pulse shaper is the input of the converter. Phie.1