RU1827718C - Decoder of pulse-time codes - Google Patents

Abstract

The invention relates to automation, computer engineering, radio engineering, communications, and in particular to pulse code sequence decoding devices, and can be used in information processing devices. The time code decoder contains the first 1 and second 2 p-bit shift registers, an inverter 3, an OR element 4, a first multiplexer 5, a code shaper 6, a first 7 and a second 8 shapers, an And 9 element and a second 10 multiplexer. An object of the invention is to simplify a decoder. The invention makes it possible to decode the input pulse sequence with high accuracy and vary the code interval over a wide range. 2 ill.

Description

Output

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The invention relates to automation, computer engineering, radio engineering, communications, and in particular to devices for decoding pulse sequence codes, and can be used in information processing devices.

The purpose of the invention is to simplify a decoder.

Figure 1 shows the functional diagram of the decoder; Fig. 2 is a timing chart explaining the principle of operation of the decoder.

The time code decoder comprises first 1 and second 2-bit shift registers, an inverter 3, an OR element 4, a first multiplexer 5, a code shaper 6, a first 7 and a second 8 shapers, an And 9 element and a second 10 multiplexer.

The decoder works as follows.

Pulses of the meander type arrive at the clock input of the decoder. At the output of the inverter 3 there will be a meander shifted relative to the input by time

t T / 2,

where T is the pulse repetition period.

Further, these meanders arrive at the clock inputs of the first 1 and second 2 shift registers. At the same time, the signal to be decrypted arrives at the combined information outputs of these registers and is recorded in the corresponding registers, and then, under the influence of clock pulses, it is shifted and appears at the outputs of the registers after a time T determined by the formula

T CT)

where K is the number corresponding to the register bit number.

From the outputs of the shift registers, the signals are fed to the corresponding inputs of the multiplexers 5 and 10, and then to the inputs of the OR elements 4. To the second input of the And 9 element, signals from the output of the register, which are selected by the multiplexer 5 and 10, pass through the second shaper 8 using sensor 6 delay code. The first 7 and second 8 shapers form signals of a certain duration under the influence of signals arriving at their inputs. The first 7 shaper generates short pulses from the input signals, the second 8 shaper pulses, the duration of which is determined by the error of the DT digital delay (the first 1 and second 2 shift registers, multiplexers 5 and 10 and the OR element 4) and can be determined as follows the formula:

gF1 2 DT.

$ Signals are generated at the output of the decoder, from the coinciding in time on the first and second inputs of the element And 9, i.e. delayed current signals for a certain time i, which will correspond to a certain code interval.

The signal at the output of the device will be held for a time T Mt which corresponds to the number code Ms in the delay code 6.

Figure 2 shows diagrams explaining the principle of operation of the device. From diagram 11 it is seen that the signal supplied to the input of the device can have different durations.

Diagrams 12 and 13 show meanders arriving at the clock inputs.

first and second shift registers, and on

diagrams 14 and 15 signals at the outputs of the shift register.

Diagram 16 shows the output signals of an OR element for one of the selected code slots.

Diagrams 17 and 19 show the signals at the outputs of the second 8 and first 7 shapers.

Diagram 18 shows the input5 signals of the decoder arriving at its input after time t + T, where T is the time corresponding to the code interval.

The diagram 20 shows the output signals of the element And 9.

From the diagram it is seen that pulses 22 and

23 are recorded in one address (cell) of the second register (22-2) and the first register (23-1), respectively (see diagrams 15 and 14), because intersect with one recording front (highlighted

5 bold).

It can be seen from the diagram that when the input pulse 24 is written to the device, the number of intersections of the input pulse by the write front is p 2. This means that the pulse is recorded in two addresses (see, 24-1 and 24-2).

From the outputs of the registers, pulses 22-2, 23-1, 24-1 and 24-2 through the multiplexers are fed to the OR element, where they are combined at its output (see pulses 22-3, 23-3 and

5 24-3).

From the diagram 20 it follows that at the output of the And 9 element there will be pulses that are generated from the pulses that coincided on the And 9 element, which came from the outputs of the multiplexers through the OR element to

the input of the first driver and pulses generated by the second driver.

Pulse 23 is not at the output of the decoder, because at time t + T, there is no signal similar to it at the decoder input.

Thus, the use of the claimed technical solution makes it possible to decode the input pulse sequence with high accuracy and change the code interval in a wide range, while reducing hardware and power costs. This is achieved by dividing the input pulse sequence into two streams, followed by combining them using multiplexers and OR elements, which distinguishes the proposed technical solution from the prototype device.

Claims (1)

The claims A time code decoder comprising a first shift register, the clock input of which is combined with the inverter input and is a clock input the decoder, the inverter output is connected to the clock input of the second shift register, the information inputs of the shift registers are combined with the input of the first pulse shaper and are the information input of the decoder, the second pulse shaper, the output of which and the output of the first pulse shaper are connected to the corresponding inputs 0 AND element, OR element, code generator, the outputs of which are connected to the address inputs of the first multiplexer, characterized in that, in order to simplify the decoder, a second 5 multiplexer, the output of which and the output of the first multiplexer are connected to the corresponding inputs of the OR element, the output of which is connected to the input of the second pulse shaper, the outputs of the first and second shift registers are connected to the information inputs of the same multiplexers, the address inputs of the second multiplexer are connected to the outputs of the code shaper, output element And is the output of the decoder. Fig i