SU1640826A1 - Manchester code adaptive decoder - Google Patents

Abstract

The invention relates to automation and computing and can be used in data transmission equipment to decode Manchester code in a wide range of input data frequencies. The purpose of the invention is to simplify the device and improve the accuracy of the restoration of clock-frequency. The device contains a pulse-to-code converter 1, a delay control register 2, a mode selection switch 3, a faded 4 indications, a shaper 5 transitions, an AND-NE 6 element, a pulse counter 7, triggers 8, 9, control inputs 10, 11 devices. 3 il.

Description

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The invention relates to automation and computing and can be used in data transmission equipment.

The purpose of the invention is to simplify the device and improve the accuracy of clock recovery.

FIG. 1 is a functional diagram of the device; FIG. 2 - functional diagram of the pulse width to code converter; : -; in fig. 3 is a functional register delay control register.

Adaptive device contains. a pulse width to code converter 1, a delay control register 2, a mode selection switch 3, a display unit 4, a jumper shaper 5, an AND-NE element 6, e pulse counter 7, triggers 8, 9, control inputs 10, 11 of the device.

The pulse width converter 1 into a code is designed to convert the clock pulse duration into a digital binary equivalent and contains a generator of 12 pulses (FIG. 2), 1K triggers 13-15 a sensor 16 of the incoming data, elements 17, 18 and a quartz oscillator 19 of pulses.

The delay control register 2 is designed to store the digitally binary equivalent of the speed of the incoming data and contains an AND 20 control (Fig. 3) and a pulse counter 21.

The mode select switch 3 is for manually selecting the pe-i control press of the adaptive device. The display unit 4 is intended for visual observation of the data transmission rate. The shaper 5 transitions are intended to generate short pulses at the moments of the input signal level shift (moments of transition from low to high and vice versa). The element AND-NOT 6 is designed to form a pulse, in which the zeroing of the trigger 8 occurs and the counter 7 goes into recording mode.

The device operates in one of three modes determined by the position of the mode selector switch 3.

The first control mode is performed on the input bus 10, to which the digital equivalent comes from an external computer.

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The second control mode is manual and is performed on the input bus 11, to which the required digital-1 equivalent is fed.

The third control mode is automatic and is implemented by the delay control register 2.

The input data contains a clock signal, which is a sequence of units encoded in the Manchester code.

The sync signal comes from the information input of the device to the pulse width converter 1 into a code which, with the help of the delay control register 2, converts the sync pulse width to a digital equivalent supplied to the parallel recording inputs of the pulse counter 7. The digital equivalent of the sync pulse duration determines the optimal delay of the signal from the overflow output of the pulse counter 7 to the set trigger input 8.

The digital equivalent is stored in delay control register 2 until the end of the transmission unit.

After the end of the transmission, the converter 1 of the pulse duration into the code automatically clears the delay control register 2 and waits for the reception of the clock signal of the next data transfer unit. This process is repeated as each new input data block arrives.

The range of possible data rates is determined by the width of the pulse counter 7 and the generator frequency 12 pulses of the converter 1 of the pulse duration into a code.

Pulse generator 12 is a continuous frequency generator that is not synchronized with the frequency of the input data stream. When the clock signal arrives from the information input of the adaptive device to the pulse width converter 1 in the code, when there is a high signal level at the output of the generator 12, the trigger edges 13, 14 are set to one on the trailing edge of the clock signal pulse. When setting the signal at the output of the generator 12 to the zero state on the trailing edge of the following

the clock pulse trigger 13 is set to the zero state. Then, after one period of the trailing edge of the clock signal, the trigger 14 is set to the zero state.

The signal from the direct output of the trigger 14 and the signal from the inverse output of the trigger 13, as well as the signal from the information input of the adaptive device and the signal from the inverse output of the trigger 15 arrive at the inputs of the element 17. The input clock signal from the information input of the device enters the input of the incoming data counter, representing an integrating RC-chain and current amplifier with direct and inverse outputs.

After the time determined by the speed of response of the sensor 16 of the incoming data, a single level signal is set at its direct output. This signal is fed to the I-input of the trigger 15, the installation input of which receives a signal from the inverse output of the sensor 16 incoming data. After setting a single level at the output of the sensor 16, the incoming data at the I input of the third IK flip-flop 15 sets a single signal level, and at the R input it sets the zero level. In this case, when the next pulse arrives from the output of the element 17, the pulse level at the inverse output of the trigger 15 is set to zero, which is maintained for the entire decoding time. The signal from the output of the element And 1 7 also arrives at the first input of the element And 18. The second input of the element And 18 receives short pulses from the crystal oscillator 19. The pulse from the output of the element And 18 is a pulse from the output of the element And 17 f filled with short pulses output of the crystal oscillator 19. The formed pulse sequence from the output of the element And 18 is fed to the clock input of the counter 21 pulses of the delay control register 2.

The number of short pulses arriving from the crystal oscillator 19 over a time equal to the duration of the clock pulse is counted by the counter 21 and is set at its outputs as a digital binary signal.

equivalent. The installation input of the counter 21 pulses goes sig-. , cash from the output of the element 20. At the entrances

The signals from the And 20 element come from the direct output of the trigger 13 and from the inversion output of the trigger 15. As the inverse output of the trigger 15 during the entire decoding period

0 is set to zero, then the transition of the counter 21 pulses of the register 2 control delay to the zero state cannot occur during this entire time.

5 After the transfer is completed and the time required to complete the transients in the sensor 16 of the incoming data from converter 1, a unit level is set at the inverse output of the sensor 16, which establishes a single signal level at the inverse output of the trigger 15 of converter 1. the output of the flip-flop 13 of a single signal level at the output of the element And 20 of the delay control register 2 is set to a single level, upon arrival of which the counter 21 of the pulse 0 is set to hilar condition.

When the input data is decoded at the output of the crossover generator 5, short pulses are generated at the time of the input signal level change. These pulses through the element AND NOT 6 arrive at the clock input of the trigger 8 and the installation input of the counter 7. At the same time on the inverse output

0, the trigger 8 is set to zero, and the digital binary equivalent of the speed of the incoming data is recorded in counter 7. At the clock input of the counter 7, they receive 5 pulses from the output of the quartz oscillator 19 of the converter 1. The counter 7 operates in the subtraction mode. When counter 7 counts to zero, from its output overflow to the installation

0, the input of the trigger 8 receives a short pulse, with the arrival of which a zero level is set at the direct output of the trigger 8.

By choosing the time of occurrence of a pulse at the output of the overflow of the counter 7, equal to half the period of the following input data, the effect of pulses is eliminated,

at the output of the trigger 8 at the time of changing the bits of the input information. At the forward output of the trigger 8, clock pulses are formed, separated from the input data. The input data is decrypted using the trigger 9, the clock input of which is fed to the clock input, and the input data is sent to the information input. Thus, at the output of flip-flop 9, a pre-determined binary sequence of input data is formed.

The device has less hardware costs due to the elimination of delay elements, permanent storage, a decoder, and also provides a higher accuracy of clock recovery.

Claims (1)

Claims 25 The adaptive Manchester code decoding device containing the NAND element, the display unit, the first trigger, the direct output of which is the clock output of the device, the pulse duration converter into the code, the first, second and third outputs of which are connected respectively to the first, second and the third is named after the inputs of the delay control register, the outputs of which are connected to the first inputs of the switch five 0 0 five five The mode, the second and third inputs of which are respectively the high and low control inputs of the device, the input of the pulse width to code converter is an information input of the device, characterized in that, in order to simplify it and improve the accuracy of the clock frequency recovery, driver of transitions, pulse counter and second trigger, information input of which is combined with the input of driver of transitions and connected to the information found device, clock input connected to clock cycles th output of the device, the setup input is to the first input of the delay control register, the output of the junction generator is connected to the first input of the NAND element, the second input of which is connected to the inverse output of the first trigger, the output of the NAND element is connected to the setting input pulse counter and is connected to the clock input of the first trigger, the clock input of the pulse counter is connected to the fourth output of the pulse width to code converter, the information inputs of the pulse counter are combined with the inputs of the display unit and Keys to the outputs of selector switch, the pulse counter overflow output is connected to input of the first mounting latch, the output of the second flip-flop is a data output device. / 2 TK 14 sixteen P 2 P 18 nineteen c 21